參數(shù)資料
型號(hào)： ST72F611F1B1
英文描述： 64Mb EDO/FPM - OBSOLETE
中文描述： ST7的-低速USB 8 - 3端點(diǎn)位MCU。閃存。內(nèi)徑。水分散粒劑。定時(shí)器
文件頁數(shù)： 38/161頁
文件大?。?/td> 2070K
代理商： ST72F611F1B1
ST72324
132/161
EMC CHARACTERISTICS (Cont’d)
12.7.3.2 Static and Dynamic Latch-Up
s
LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin) and a current injection (applied to
each input, output and configurable I/O pin) are
performed on each sample. This test conforms
to the EIA/JESD 78 IC latch-up standard. For
more
details,
refer
to
the
AN1181
ST7
application note.
s
DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 71. For
more
details,
refer
to
the
AN1181
ST7
application note.
12.7.3.3 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
Electrical Sensitivities
Figure 71. Simplified Diagram of the ESD Generator for DLU
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
Symbol
Parameter
Conditions
Class 1)
LU
Static latch-up class
TA=+25°C
TA=+85°C
TA=+125°C
A
DLU
Dynamic latch-up class
VDD=5.5V, fOSC=4MHz, TA=+25°C
A
RCH=50M
RD=330
CS=150pF
ESD
HV RELAY
DISCHARGE TIP
DISCHARGE
RETURN CONNECTION
GENERATOR 2)
ST7
VDD
VSS
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