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| 型號： | ST72651R6 |
| 英文描述： | SODIMM MEMORY MODULE, 64MB, INDUSTRIAL TEMP |
| 中文描述： | ST7的-低功耗。全速USB 8位32K快閃微控制器。 5K內(nèi)存。閃存卡的I /樓計時器。脈寬調(diào)制。 ADC的。的I2C |
| 文件頁數(shù)： | 18/166頁 |
| 文件大?。?/td> | 2089K |
| 代理商： | ST72651R6 |
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ST7265x
114/166
IC SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.7 Register Description
I2C CONTROL REGISTER (CR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE
Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master capability
Notes:
– When PE=0, all the bits of the CR register and
the SR register except the Stop bit are reset. All
outputs are released while PE=0
– When PE=1, the corresponding I/O pins are se-
lected by hardware as alternate functions.
– To enable the I2C interface, write the CR register
TWICE with PE=1 as the first write only activates
the interface (only PE is set).
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = START
Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Start condition is sent
(with interrupt generation if ITE=1).
– In master mode:
0: No start generation
1: Repeated start generation
– In idle mode:
0: No start generation
1: Start generation when the bus is free
Bit 2 = ACK
Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after a data byte is re-
ceived
Bit 1 = STOP
Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0) or when the Stop condition is sent.
– In Master mode only:
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent.
Bit 0 = ITE
Interrupt enable.
This bit is set and cleared by software and cleared
by hardware when the interface is disabled
(PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 4 for the relationship between the
events and the interrupt.
SCL is held low when the SB or BTF flags or an
EV2 event (See Figure 68) is detected.
70
0
PE
0
START
ACK
STOP
ITE
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PDF描述 |
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| ST72651R6T1 | ST7 - LOW-POWER. FULL-SPEED USB 8-BIT MCU WITH 32K FLASH. 5K RAM. FLASH CARD I/F. TIMER. PWM. ADC. I2C |
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相關(guān)代理商/技術(shù)參數(shù) |
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