參數(shù)資料
型號： ST72651R6
英文描述： SODIMM MEMORY MODULE, 64MB, INDUSTRIAL TEMP
中文描述： ST7的-低功耗。全速USB 8位32K快閃微控制器。 5K內(nèi)存。閃存卡的I /樓計時器。脈寬調(diào)制。 ADC的。的I2C
文件頁數(shù)： 105/166頁
文件大小： 2089K
代理商： ST72651R6
ST7265x
43/166
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 30.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
7.4 CONCURRENT & NESTED MANAGEMENT
The following Figure 31 and Figure 32 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 32. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Figure 31. Concurrent Interrupt Management
Figure 32. Nested Interrupt Management
MAIN
IT4
IT2
IT1
TLI
IT1
MAIN
IT0
I1
HA
RD
WA
RE
P
R
IO
RIT
Y
SOFTWARE
3
3/0
3
11
11 / 10
11
RIM
IT
2
IT
1
IT
4
TLI
IT
3
IT
0
IT3
I0
10
PRIORITY
LEVEL
US
ED
S
TACK
=
1
0
BYT
ES
MAIN
IT2
TLI
MAIN
IT0
IT2
IT1
IT4
TLI
IT3
IT
0
HA
RDWA
R
E
P
R
IO
RIT
Y
3
2
1
3
3/0
3
11
00
01
11
RIM
IT1
IT4
IT1
IT2
IT3
I1
I0
11 / 10
10
SOFTWARE
PRIORITY
LEVEL
USE
D
S
T
ACK
=
2
0
B
YTE
S
1
相關(guān)PDF資料
PDF描述
ST72651R6T1 ST7 - LOW-POWER. FULL-SPEED USB 8-BIT MCU WITH 32K FLASH. 5K RAM. FLASH CARD I/F. TIMER. PWM. ADC. I2C
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