參數(shù)資料
型號: ST72651R6
英文描述: SODIMM MEMORY MODULE, 64MB, INDUSTRIAL TEMP
中文描述: ST7的-低功耗。全速USB 8位32K快閃微控制器。 5K內存。閃存卡的I /樓計時器。脈寬調制。 ADC的。的I2C
文件頁數(shù): 122/166頁
文件大?。?/td> 2089K
代理商: ST72651R6
ST7265x
59/166
WATCHDOG TIMER (Cont’d)
11.1.4 Software Watchdog Option
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
11.1.5 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
11.1.6 Low Power Modes
Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as Input before executing the HALT instruction.
The main reason for this is that the I/O may be
wrongly configured due to external interference
or by an unforeseen logical condition.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the I bits in the
CC register to allow interrupts, the user may
choose to clear all pending interrupt bits before
executing the HALT instruction. This avoids en-
tering other peripheral interrupt routines after ex-
ecuting the external interrupt routine
corresponding to the wake-up event (reset or ex-
ternal interrupt).
11.1.7 Interrupts
None.
Mode
Description
WAIT
No effect on Watchdog.
HALT
If the WDGHALT bit in the MISCR3 register is set, Halt mode can be used when the watchdog
is enabled. When the oscillator is stopped, the WDG stops counting and is no longer able to
generate a reset until the microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case
of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state).
Note: In USB mode, and in Suspend mode, a reset is not generated by entering Halt mode
1
相關PDF資料
PDF描述
ST72651R6T1 ST7 - LOW-POWER. FULL-SPEED USB 8-BIT MCU WITH 32K FLASH. 5K RAM. FLASH CARD I/F. TIMER. PWM. ADC. I2C
ST72652R4T1 ST7 - LOW-POWER. FULL-SPEED USB 8-BIT MCU WITH 32K FLASH. 5K RAM. FLASH CARD I/F. TIMER. PWM. ADC. I2C
ST7271J1B1 8-BIT MICROCONTROLLER
ST7271N1B1 8-BIT MICROCONTROLLER
ST7271N2 Microcontroller
相關代理商/技術參數(shù)
參數(shù)描述
ST7265X-EVAL/MS 制造商:STMicroelectronics 功能描述:ST6 EVAL BD - Bulk
ST7265X-EVAL/PFD 制造商:STMicroelectronics 功能描述:USB FLASH EVAL - Bulk
ST7266 制造商:6940 功能描述:ST7266
ST7267C8T1L 制造商:STMicroelectronics 功能描述:
ST72681/R12 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE BUS-POWERED USB 2.0 FLASH DR - Trays