
ST7265x
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POWER SUPPLY MANAGEMENT (Cont’d)
6.4.5 Register Description
POWER CONTROL REGISTER (PCR)
Reset Value: 0000 0000 (00h)
Bit 7 = ITPF
Voltage Input Threshold Plus Flag
This bit is set by hardware when USBVDD rises
over USBVIT+ and cleared by hardware when US-
BVDD drops below USBVIT+.
0: USBVDD < USBVIT+
1:USBVDD > USBVIT+
Bit 6 = ITMF
Voltage Input Threshold Minus Flag
This bit is set by hardware when USBVDD rises
over USBVIT- and cleared by hardware when US-
BVDD drops below USBVIT-.
0: USBVDD < USBVIT-
1:USBVDD > USBVIT-
Bit 5 = PLG
USB Plug/Unplug detection.
This bit is set by hardware when it detects that the
USB cable has been plugged in. It is cleared by
hardware when the USB cable is unplugged. (De-
tection happens when USBVDD rises over USB-
VIT+ or when USBVDD drops below USBVIT-). If
the PLGIE bit is set, the rising edge of the PLG bit
also generates an interrupt request.
0: USB cable unplugged
1: USB cable plugged in
Bit 4 = PLGIE
USB Plug/Unplug Interrupt Enable.
This bit is set and cleared by software.
0: Single supply mode: PLG interrupt disabled.
1: Dual supply mode: PLG interrupt enabled (gen-
erates an interrupt on the rising edge of PLG).
Bit 3:2 = VSET[1:0]
Voltage Regulator Output
Voltage.
These bits are set and cleared by software to se-
lect the output voltage of the on-chip voltage regu-
lator (for the VDDF output).
Bit 1 = DETEN
USB Voltage Detector Enable.
This bit is set and cleared by software. It is used to
power-off the USB voltage detector in Stand-alone
mode.
0: The USB voltage detector is enabled.
1: The USB voltage detector disabled (ITPF, ITMF
and PLG bits are forced high)
Bit 0 = REGEN
Voltage Regulator Enable.
This bit is set and cleared by software.
0: The regulator is completely shutdown and no
current is drawn from the power supply by the
voltage reference.
1: The on-chip voltage regulator is powered-on.
70
ITPF
ITM
F
PLG
IE
VSE
T1
VSE
T0
DET
EN
REG
EN
VSE
T1
VSE
T0
Voltage output of the regulator
00
3.5V
01
3.4V
1
0
3.3V
11
2.8V
1