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參數(shù)資料
| 型號： | ST72372 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) |
| 中文描述： | 8 - 16K的光碟/雙層/存儲器，512字節(jié)RAM，ADC和DAC的器（PWM），定時器，IIC和脊髓損傷（8位微控制器（8米）位MCU） |
| 文件頁數(shù)： | 76/94頁 |
| 文件大?。?/td> | 642K |
| 代理商： | ST72372 |
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ST72371/ST72372
8-BIT A/D CONVERTER (ADC)
(Cont’d)
4.7.4 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = COCO Conversion Complete.
This bit is set by hardware. It is cleared by soft-
ware reading the result in theDR register or writing
to the CSR register.
0: Conversion is not complete.
1: Conversion can be read from the DR register.
Bit 6 = Reserved. Must always be cleared.
Bit 5 = ADON A/D converter On.
This bit is set and cleared by software.
0: A/D converter is switched off.
1: A/D converter is switched on.
Note: a typically 30
μ
s delay time is necessary for
the ADC to stabilize when the ADON bit is set.
Bit 4 = Reserved. Forced by hardware to 0.
Bit 3 = Reserved. Must always be cleared.
Bits 2-0: CH2-CH0 Channel Selection.
These bits are set and cleared by software. They
select the analog input to convert.
Table 21.
Channel Selection
(*The number of pins varies according to the de-
vice. Refer to the device pinout).
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = AD7-AD0 Analog Converted Value.
This register contains the converted analog value
in the range 00h to FFh.
Reading this register reset the COCO flag.
Table 22.ADC Register Map
7
0
COCO
-
ADON
0
-
CH2
CH1
CH0
Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
CH2
0
0
0
0
1
1
1
1
CH1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
0
1
0
1
7
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Address
(Hex.)
Register
Name
7
6
5
4
3
2
1
0
0B
CSR
COCO
-
ADON
0
-
CH2
CH1
CH0
0A
DR
AD7 .. AD0
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