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參數(shù)資料
| 型號： | ST72372 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) |
| 中文描述： | 8 - 16K的光碟/雙層/存儲器，512字節(jié)RAM，ADC和DAC的器（PWM），定時器，IIC和脊髓損傷（8位微控制器（8米）位MCU） |
| 文件頁數(shù)： | 72/94頁 |
| 文件大?。?/td> | 642K |
| 代理商： | ST72372 |
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ST72371/ST72372
PWM/BRM GENERATOR (Cont’d)
4.6.4 Register Description
4.6.4.1 10-bit PWM/BRM REGISTERS
On a channel basis, the 10 bits are separated into
two data registers:
– A 6-bit PWM register corresponding to the binary
weight of the PWM pulse.
– A 4-bit BRM register defining the intervals where
an incremental pulse isadded to the beginning of
the original PWM pulse. Two BRM channel val-
ues share the same register.
Note:
The number of PWM and BRM channels
available depends on the device. Refer to the de-
vice pin description and register map.
PWM[1:8] REGISTERS
Read/Write
Reset Value 1000 0000 (80h)
Bit 7 = Reserved (read as “1”)
Bit 6 =
POL
Polarity Bit.
When POL is set, output signal polarity is inverse;
otherwise, no change occurs.
Bits 5:0 =
P[5:0]
PWM Pulse Binary Weight for
channel i .
BRM REGISTERS
BRM21 (Channels 2 + 1)
BRM43 (Channels 4 + 3)
BRM65 (Channels 6 + 5)
BRM87 (Channels 8 + 7)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:4 =
B[7:4]
BRM Bits (channel i+1)
Bits 3:0 =
B[3:0]
BRM Bits (channel i)
4.6.4.2 12-bit PWM/BRM REGISTERS
The 12 bits are separated into two data registers:
– A 6-bitPWM register corresponding to thebinary
weight of the PWM pulse.
– A 6-bit BRM register defining the intervals where
incremental pulses are added to thebeginning of
the original PWM pulse.
PWM0 REGISTER
Read/ Write
Reset Value: 1000 0000 (80h)
Bit 7 = Reserved (read as “1”)
Bit 6 =
POL
Polarity Bit.
When POL is set, output signal polarity is inverse;
otherwise, no change occurs.
Bits 5:0 =
P[5:0]
PWM Pulse Binary Weight
BRM0 REGISTER
Read/ Write
Reset Value: 1100 0000 (C0h)
Bits 7:6 = Unused
Bits 5:0 =
B[5:0]
BRM Bits
7
0
1
POL
P5
P4
P3
P2
P1
P0
7
0
B7
B6
B5
B4
B3
B2
B1
B0
7
0
1
POL
P5
P4
P3
P2
P1
P0
7
0
1
1
B5
B4
B3
B2
B1
B0
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