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參數(shù)資料
| 型號： | ST72372 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) |
| 中文描述： | 8 - 16K的光碟/雙層/存儲(chǔ)器，512字節(jié)RAM，ADC和DAC的器（PWM），定時(shí)器，IIC和脊髓損傷（8位微控制器（8米）位MCU） |
| 文件頁數(shù)： | 75/94頁 |
| 文件大小： | 642K |
| 代理商： | ST72372 |
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ST72371/ST72372
8-BIT A/D CONVERTER (ADC)
(Cont’d)
4.7.3 Functional Description
The high level reference voltage V
DDA
must be
connected externally to the V
DD
pin. The low level
reference voltage V
SSA
must be connected exter-
nally to the V
SS
pin. In some devices (refer to de-
vice pin out description) high and low level refer-
ence voltages are internally connected to the V
DD
and V
SS
pins.
Conversion accuracy may therefore be degraded
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
Characteristics
The conversion is monotonic meaning the result
never decreases if the analog input does not and
never increases if the analog input does not.
If input voltage is greater than or equal to V
DD
(voltage reference high) then results = FFh (full
scale) without overflow indication.
If input voltage
≤
V
SS
(voltage reference low) then
the results = 00h.
The conversion time is 64 CPU clock cycles in-
cluding a sampling time of 31.5 CPU clock cycles.
The A/D converter is linear and the digital result of
the conversion is given by the formula:
Where Reference Voltage is V
DD
- V
SS
.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
Procedure
Refer to the CSR and SR registersSection 0.1.4
for the bit definitions.
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the I/O
ports chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
– Select the CH2 to CH0 bits to assign the ana-
log channel to convert. Refer toTable 1.
– Set the ADON bit. Then the A/D converter is
enabled after a stabilization time (typically 30
μ
s). It then performs a continuous conversion
of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register.
A write to the CSR register aborts the current con-
version, resets the COCO bit and starts a new
conversion.
Notes: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
The A/D converter is not affected by WAIT mode.
When the MCU enters HALT mode with the A/D
converter enabled, the converter is disabled until
the HALT mode is exited and the start-up delay
has elapsed. A stabilisation time is also required
before accurate conversions can be performed.
Digital result =255 * Input Voltage
Reference Voltage
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