- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382552 > ST72372 (意法半導(dǎo)體) 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) PDF資料下載
參數(shù)資料
| 型號(hào)： | ST72372 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit MCUs with 16K ROM/OTP/EPROM, 512 Bytes RAM, ADC, DAC (PWM), Timer, IIC and SCI(8位微控制器(8M)) |
| 中文描述： | 8 - 16K的光碟/雙層/存儲(chǔ)器，512字節(jié)RAM，ADC和DAC的器（PWM），定時(shí)器，IIC和脊髓損傷（8位微控制器（8米）位MCU） |
| 文件頁數(shù)： | 50/94頁 |
| 文件大?。?/td> | 642K |
| 代理商： | ST72372 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
50/94
ST72371/ST72372
I C BUS INTERFACE
(Cont’d)
4.4.4.2 Master Mode
To switch from default Slave mode to Master
mode a Start condition generation is needed.
Start condition and Transmit Slave address
Setting the START bit while the BUSY bit is clea-
red causes the interface to switch to Master mode
(M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
– The EVF and SB bits are set by hardware with
an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write in the DR register with the
Slave address byte,
holding the SCL line low
(see Figure 3 Transfer sequencing EV5).
Then the slave address byte is sent to the SDA
line via the internal shift register.
After completion of this transfer (and acknowledge
from the slave if the ACK bit is set):
– The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Then the master waits for a read of the SR1 regis-
ter followed by a write inthe CR register (for exam-
ple set PE bit),
holding the SCL line low
(see Fi-
gure 3 Transfer sequencing EV6).
Next the master must enter Receiver or Transmit-
ter mode.
Master Receiver
Following the address transmission and after SR1
and CR registers have been accessed, themaster
receives bytes from the SDA line into theDR regis-
ter via the internal shift register. After each byte
the interface generates in sequence:
– Acknowledge pulse if if the ACK bit is set
– EVF and BTF bitsare set by hardware with anin-
terrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 re-
gister followed by a read of the DR register,
hol-
ding the SCL line low
(see Figure 3 Transfer se-
quencing EV7).
To close the communication: before reading the
last byte from the DR register, set the STOP bit to
generate the Stop condition. The interface goes
automatically back to slave mode (M/SL bit clea-
red).
Note:
In order to generate the non-acknowledge
pulse after the last received data byte, the ACK bit
must be cleared just before reading the second
last data byte.
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register,
holding the
SCL line low
(see Figure 3 Transfer sequencing
EV8).
When the acknowledge
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
is set.
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gene-
rate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
bit is received, the
Error Cases
–
BERR
: Detection of a Stop or a Start condition
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
–
AF
: Detection of a non-acknowledge bit. In this
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the START or STOP bit.
–
ARLO:
Detection of an arbitration lost condition.
In thiscase the ARLO bitis set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slavemode (theM/SL
bit is cleared).
Note
: In all these cases, the SCL line is not held
low; however, the SDA line can remain low due to
possible 0 bits transmitted last. It is then neces-
sary to release both lines by software.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72681 | USB 2.0 HIGH-SPEED 8-BIT MCU FLASH DRIVE CONTROLLER |
| ST72753L4 | 8-BIT MCU FOR MONITORS WITH UP TO 32K ROM, 1K RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I2C |
| ST72753L5 | 8-BIT MCU FOR MONITORS WITH UP TO 32K ROM, 1K RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I2C |
| ST72753L6 | 8-BIT MCU FOR MONITORS WITH UP TO 32K ROM, 1K RAM, ADC, TIMER, SYNC, PWM/BRM, DDC/DMA & I2C |
| ST72C171 | 8-BIT MCU with 8K FLASH, ADC, WDG, SPI, SCI, TIMERS SPGAs Software Programmable Gain Amplifiers, OP-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72372J4B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH 16K ROM/OTP/EPROM,512 BYTES RAM, ADC, DAC (PWM), TIMER, I2C AND SCI |
| ST72372J4T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH 16K ROM/OTP/EPROM,512 BYTES RAM, ADC, DAC (PWM), TIMER, I2C AND SCI |
| ST72389BW | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH NESTED INTERRUPTS, DOT MATRIX LCD, ADC, TIMERS, PWM-BRM, SPI, SCI, IC, CAN INTERFACES |
| ST72389BW4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH NESTED INTERRUPTS, DOT MATRIX LCD, ADC, TIMERS, PWM-BRM, SPI, SCI, IC, CAN INTERFACES |
| ST72389BW4/XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCONTROLLER|8-BIT|ST72 CPU|CMOS|QFP|128PIN|PLASTIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。