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參數(shù)資料
| 型號： | ST68C454 |
| 廠商： | Exar Corporation |
| 英文描述： | QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| 中文描述： | 四通用異步接收/發(fā)送器（UART） |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 378K |
| 代理商： | ST68C454 |
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ST16C454/68C454
17
Rev. 3.20
LCR BIT-5 = logic 0, parity is not forced. (normal
default condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
LCR
Bit-5
LCR
Bit-4
LCR
Bit-3
Parity selection
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity 1
Forced parity 0
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
Not used - Initialized to a logic 0.
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
MCR BIT-2:
This bit is used in the Loop-back mode only. In the
loop-back mode this bit is use to write the state of the
modem -RI interface signal via -OP1.
MCR BIT-3: (
Used to control the modem -CD signal
in the loop-back mode.)
Logic 0 = Forces INT (A-D) outputs to the three state
mode during the 16 mode. (normal default condition)
In the Loop-back mode, sets -OP2 (-CD) internally to
a logic 1.
Logic 1 = Forces the INT (A-D) outputs to the active
mode during the 16 mode. In the Loop-back mode,
sets -OP2 (-CD) internally to a logic 0.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT 5-7:
Not used - Initialized to a logic 0.
Line Status Register (LSR)
This register provides the status of data transfers
between. the 454 and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register. (normal
default condition)
Logic 1 = Data has been received and is saved in the
receive holding register.
LSR BIT-1:
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tional data arrives while the RHR is full. In this case the
previous data in the shift register is overwritten. Note
that under this condition the data byte in the receive
shift register is not transferred into the RHR, therefore
the data in the RHR is not corrupted by the error.
LSR BIT-2:
Logic 0 = No parity error. (normal default condition)
Logic 1 = Parity error. The receive character does not
have correct parity information and is suspect. In the
RHR mode, this error is associated with the character
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST68C554 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD UART WITH 16-BYTE FIFOS |
| ST68C554CJ68 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST68C554CJ68-F | 功能描述:UART 接口集成電路 SIGNALS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST68C554IJ68 | 制造商:Exar Corporation 功能描述: |
| ST68C554IJ68-F | 功能描述:UART 接口集成電路 SIGNALS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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