參數(shù)資料
型號(hào): ST68C454
廠商: Exar Corporation
英文描述: QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
中文描述: 四通用異步接收/發(fā)送器(UART)
文件頁(yè)數(shù): 14/30頁(yè)
文件大?。?/td> 378K
代理商: ST68C454
ST16C454/68C454
14
Rev. 3.20
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 454 internal registers. The assigned bit
functions are more fully defined in the following paragraphs.
Table 6, ST16C454 INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *5
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Register Set
0
0
0
RHR[XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
0
THR[XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
1
IER[00]
0
0
0
0
modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
receive
holding
register
0
1
0
ISR[01]
0
0
0
0
INT
priority
bit-2
INT
priority
bit-1
INT
priority
bit-0
INT
status
0
1
1
LCR[00]
divisor
latch
enable
set
break
set
parity
even
parity
parity
enable
stop
bits
word
length
bit-1
word
length
bit-0
1
0
0
MCR[00]
0
0
0
loop
back
-OP2/
INTx
enable
-OP1
-RTS
-DTR
1
0
1
LSR[60]
0
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
0
MSR[X0]
CD
RI
DSR
CTS
delta
-CD
delta
-RI
delta
-DSR
delta
-CTS
1
1
1
SPR[FF]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
Special Register set: Note *2
0
0
0
DLL[XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
1
DLM[XX]
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
Note *
2
: The Special register set is accessible only when LCR bit-7 is set to 1.
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