參數(shù)資料
型號(hào): ST68C454
廠商: Exar Corporation
英文描述: QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
中文描述: 四通用異步接收/發(fā)送器(UART)
文件頁(yè)數(shù): 11/30頁(yè)
文件大?。?/td> 378K
代理商: ST68C454
ST16C454/68C454
11
Rev. 3.20
Programmable Baud Rate Generator
The 454 supports high speed modem technologies
that have increased input data rates by employing
data compression schemes. For example a 33.6Kbps
modem that employs data compression may require a
115.2Kbps input data rate. A 128.0Kbps ISDN modem
that supports data compression may need an input
data rate of 460.8Kbps. The 454 can support a stan-
dard data rate of 921.6Kbps.
Single baud rate generator is provided for the trans-
mitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Gen-
erator is capable of accepting an input clock up to 24
MHz, as required for supporting a 1.5Mbps data rate.
The 454 can be configured for internal or external
clock operation. For internal clock oscillator opera-
tion, an industry standard microprocessor crystal (par-
allel resonant/ 22-33 pF load) is connected externally
between the XTAL1 and XTAL2 pins (see figure 8).
Alternatively, an external clock can be connected to
the XTAL1 pin to clock the internal baud rate generator
for standard or custom rates. (see Baud Rate Genera-
tor Programming).
The generator divides the input 16X clock by any
divisor from 1 to 2
16
-1. The 454 divides the basic
crystal or external clock by 16. Further division of this
16X clock provides two table rates to support low and
high data rate applications using the same system
design. Customized Baud Rates can be achieved by
selecting the proper divisor values for the MSB and
LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers
DLM (MSB) and DLL (LSB) provides a user capability
for selecting the desired final baud rate. The example
in Table 5 below, shows the two selectable baud rate
tables available when using a 1.8432MHz or 7.3728
MHz crystal.
Output
Baud Rate
(1.8432 MHz (7.3728 MHz
Clock)
Output
Baud Rate
User
User
DLM
Program
Value
(HEX)
DLL
16 x Clock
Divisor
(Decimal)
16 x Clock
Divisor
(HEX)
Program
Value
(HEX)
Clock)
50
300
600
1200
2400
4800
9600
19.2k
38.4k
57.6k
115.2k
200
1200
2400
4800
9600
19.2K
38.4k
76.8k
153.6k
230.4k
460.8k
2304
384
192
96
48
24
12
6
3
2
1
900
180
C0
60
30
18
0C
06
03
02
01
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
03
02
01
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