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參數(shù)資料
| 型號(hào)： | ST62T63C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI |
| 中文描述： | 8位檢察官辦公室/存儲(chǔ)器與阿微控制器/ D轉(zhuǎn)換器，安全復(fù)位，自動(dòng)重加載定時(shí)器，EEPROM和的SPI |
| 文件頁數(shù)： | 54/86頁 |
| 文件大?。?/td> | 559K |
| 代理商： | ST62T63C |
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ST62T53C/T60C/T63C ST62E60C
4.5 SERIAL PERIPHERAL INTERFACE (SPI)
The SPI peripheral is an optimized synchronous
serial interface with programmable transmission
modes and master/slave capabilities supporting a
wide range of industrystandard SPI specifications.
The SPI interface may also implement asynchro-
nous data transfer, in which case processor over-
head is limited to data transfer from or to the shift
register on an interrupt driven basis.
The SPI may be controlled by simple user soft-
ware to perform serial data exchange with low-
cost external memory, or with serially controlled
peripherals to drive displays, motors or relays.
The SPI’s shift register is simultaneously fed by
the Sin pin and feeds the Sout pin, thus transmis-
sion and reception are essentially the same proc-
ess. Suitable setting of the number of bits in the
data frame can allow filtering of unwanted leading
data bits in the incoming data stream.
The SPI comprises an 8-bit Data/Shift Register,
DSR, a Divide register, DIV, a Mode Control Reg-
ister MOD, and a Miscellaneous register, MISCR.
The SPI may be operated either in Mastermode or
in Slave mode.
Master mode is defined by the synchronous serial
clock being supplied by the MCU, by suitably pro-
gramming the clock divider (DIV register). Slave
mode is defined by the serial clock being supplied
externally on the SCK pin by the external Master
device.
For maximum versatility the SPI may be pro-
grammed to sample data either on the rising or on
the falling edge of SCK,with or without phase shift
(clock Polarity and Phase selection).
The Sin, Sout and SCK signals are connected as
alternate I/O pin functions.
For serial input operation, Sin must be configured
as aninput. For serial output operation,Sout is se-
lected as an output by programming Bit 0 of the
Miscellaneous Register: clearing this bit will set
the pin as a standard I/O line, while setting the bit
will select the Sout function.
An interrupt request may be associated with the
end of a transmission or reception cycle; this is de-
fined by programming the number of bits in the
data frame and by enabling the interrupt. This re-
quest is associated with interrupt vector #2, and
can be masked by programming the SPIE bit of
the MOD register. Since the SPI interrupt is
“ORed” with the port interrupt source, an interrupt
flag bit is available in the DIV register allowing dis-
crimination of the interrupt request.
Figure 31. SPI Block Diagram
SPI
SCK
FILTER
Sin
Sout
CPU
CYCLE
CLOCK
CLOCK
DATA BUS
8
VR001693
SHIFT
REGISTER
FILTER
DIVIDER
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST62T63CB6 | 功能描述:8位微控制器 -MCU OTP EPROM 2K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST62T63CM6 | 功能描述:8位微控制器 -MCU OTP EPROM 2K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST62T65CB3 | 制造商:STMicroelectronics 功能描述:+125C 4K OTP DIP - Rail/Tube |
| ST62T65CB6 | 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST62T65CB6 | 制造商:STMicroelectronics 功能描述:8BIT MCU OTP 4K+EEPROM 62T65 DIP |
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