參數(shù)資料
型號(hào)： ST62T63C
廠商： 意法半導(dǎo)體
英文描述： 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, SAFE RESET, AUTO-RELOAD TIMER, EEPROM AND SPI
中文描述： 8位檢察官辦公室/存儲(chǔ)器與阿微控制器/ D轉(zhuǎn)換器，安全復(fù)位，自動(dòng)重加載定時(shí)器，EEPROM和的SPI
文件頁(yè)數(shù)： 11/86頁(yè)
文件大?。?/td> 559K
代理商： ST62T63C
11/86
11
ST62T53C/T60C/T63C ST62E60C
MEMORY MAP
(Cont’d)
1.3.6
Data
(DRBR)
Address: E8h
RAM/EEPROM
Bank
Register
—
Write only
Bit 7-5 = These bits are not used
Bit 4 -
DRBR4
. This bit, when set, selects RAM
Page 2.
Bit 3-2 - Reserved. These bits are not used.
Bit 1 -
DRBR1
. This bit, when set, selects
EEPROM Page 1, when available.
Bit 0 -
DRBR0
. This bit, when set, selects
EEPROM Page 0, when available.
The selectionof the bank is madeby programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address E8h of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations.This register is used to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. The bank number has to be loaded in
the DRBR register and the instruction has to point
to the selected location as if it was in bank 0 (from
00h address to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes
:
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Care must also be taken not to change the
E
PROM page (when available) when the parallel
writing mode is set for the
E
PROM, as defined in
EECTL register.
Table 3. Data RAM Bank Register Set-up
7
0
-
-
-
DRBR
4
-
-
DRBR
1
DRBR
0
DRBR
ST62T53C
ST62T60C/E60C
ST62T63C
00
None
None
None
01
Not Available
EEPROM Page 0
EEPROM Page 0
02
Not Available
EEPROM Page 1
Not Available
08
Not Available
Not Available
Not Available
10h
RAM Page 2
RAM Page 2
RAM Page 2
other
Reserved
Reserved
Reserved
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