
ST16C1550/51
20
Rev. 3.10
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
MCR BIT-2:
In the normal mode, this bit is associated the RST
(buffered reset output) function and is enabled by bit-
5 of the IER register. The RST function is available on
28 pin ST16C1551 package only. The 48 pin
ST16C1550/51 package all provide the RST function.
While in the normal mode, the logical state of the RST
pin will follow exactly the logical state of RESET pin,
i.e., soft resets are disabled. During special mode
operation, soft resets from MCR bit 2 are ORd with
the state of the input pin, RESET. Therefore both reset
types will be seen at the RST pin.
Logic 0 = The RST output pin is a logic 0. (normal
default condition)
Logic 1 = The RST output pin is a logic 1
In the loopback mode where MCR bit-4 is a logic 1 this
bit is used to write the state of the modem -RI interface
signal.
Loopback mode, Logic 0 = sets -RI internally to a logic
1.
Loopback mode, Logic 1 = sets -RI internally to a logic
0.
MCR BIT-3
This bit controls the tri-state interrupt function or in the
loopback mode this bit is used to control the modem
-CD signal.
Logic 0 = Forces INT outputs to the tri-state mode or
sets -CD to a logic 1 in the loopback mode. (normal
default condition).
Logic 1 = Forces the INT outputs to the active mode
or sets -CD to a logic 0 in the loopback mode.
In the Loopback mode, sets -CD internally to a logic 0.
MCR BIT-4:
Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (-TX) and the receiver
input (-RX), -CTS, -DSR, -CD, and -RI are discon-
nected from the 155X I/O pins. Internally the modem
data and control pins are connected into a loopback
data configuration. In this mode, the receiver and
transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the
interrupts sources are switched to the lower four bits of
the Modem Control. Interrupts continue to be con-
trolled by the IER register.
Logic 0 = Disable loopback mode. (normal default
condition)
Logic 1 = Enable local loopback mode (diagnostics).
MCR BIT 5-6:
Not Used - initialized to a logic 0.
MCR BIT-7:
Logic 0 = No power down mode. (normal default
condition)
Logic 1 = Enable power down mode with baud rate
generator circuitry disabled.
Line Status Register (LSR)
This register provides the status of data transfers
between. the 155X and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register or FIFO.
(normal default condition)
Logic 1 = Data has been received and is saved in the
receive holding register (RHR) or FIFO.
LSR BIT-1:
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred
in the receive shift register. This happens when addi-
tional data arrives while the FIFO is full. In this case
the previous data in the shift register is overwritten.
Note that under this condition the data byte in the
receive shift register is not transferred into the FIFO,
therefore the data in the FIFO is not corrupted by the
error.