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參數(shù)資料
| 型號： | ST16C1551 |
| 廠商： | Exar Corporation |
| 英文描述： | UART with 16-Byte FIFO(通用異步接收器/發(fā)送器（帶16字節(jié)的先進先出）) |
| 中文描述： | 的UART具有16字節(jié)FIFO（通用異步接收器/發(fā)送器（帶16字節(jié)的先進先出）） |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 418K |
| 代理商： | ST16C1551 |
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ST16C1550/51
16
Rev. 3.10
E) LSR BIT-7 will show if any FIFO data errors
occurred.
IER BIT-0:
In the 16C450 mode, This interrupt will be issued when
the RHR has data or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued
when the FIFO has reached the programmed trigger
level or is cleared when the FIFO drops below the
trigger level.
Logic 0 = Disable the receiver ready (ISR level 2,
RXRDY) interrupt. (normal default condition)
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
IER BIT-1:
In the 16C450 mode, this interrupt will be issued
whenever the THR is empty and is associated with bit-
5 in the LSR register. In the FIFO modes, this interrupt
will be issued whenever the FIFO and THR are empty
Logic 0 = Disable the Transmit Holding Register
Empty (TXRDY) interrupt. (normal default condition)
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
IER BIT-2:
This interrupt will be issued whenever an receive data
error condition exists as reflected in LSR bits 1-4.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
This interrupt will be issued whenever there is a
modem status change as reflected in MSR bits 0-3.
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-:
Not Used - initialized to a logic 0.
IER BIT 5:
This bit is used to enable the enhanced features of the
155X. Enhanced features include the DMA monitor
function (TXRDY/RXRDY), the SOFT reset function,
and the power down function. When enabled (IER bit-
5 = a logic 1), a logic 1 at MCR bit will power down the
155X, the logical state of MCR bit-2 will be reflected at
the RST output pin, and TXRDY/RXRDY status will be
made available in the ISR register (bits 4-5).
Logic 0 = enable basic ST16C450 functions only.
(normal default condition).
Logic 1 = enable special mode functions in addition to
basic ST16C450 functions, i.e., enable ISR bits 4-5
(TXRDY/RXRDY), MCR bit-2 (soft reset) and MCR
bit-7 (power down) functions.
IER BIT 6-7-:
Not Used - initialized to a logic 0.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the receive FIFO trigger levels, and select
the DMA mode. The DMA, and FIFO modes are
defined as follows:
DMA MODE
Mode 0
Set and enable the interrupt for each single transmit or
receive operation, and is similar to the ST16C450
mode. Transmit Ready (-TXRDY) will generate an
interrupt when ever an empty transmit space is avail-
able in the Transmit Holding Register (THR) and
TXRDY is enabled by IER bit-5. Receive Ready (-
RXRDY) will generate an interrupt whenever the Re-
ceive Holding Register (RHR) is loaded with a charac-
ter and RXRDY is enabled by IER bit-5. Both TXRDY
and RXRDY may be viewed at any time by reading
ISR bits 4-5 respectively.
Mode 1 Set and enable the interrupt in a block mode
operation. The transmit interrupt is set when the
transmit FIFO is below the programmed trigger level.
-TXRDY, when enabled by IER bit 5, will generate an
interrupt as long as one empty FIFO location is
available. The receive interrupt is set when the re-
ceive FIFO fills to the programmed trigger level, if
enabled be IER bit-5. However the FIFO continues to
fill regardless of the programmed level until the FIFO
is full. TXRDY and RXRDY may be viewed at any time
by reading ISR bits 4-5 respectively. -RXRDY remains
a logic 0 as long as the FIFO fill level is above the
programmed trigger level.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
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| ST16C2550CP40 | Power Supply IC; Supply Voltage Max:6V; Output Voltage:1.3V; Package/Case:20-TSSOP; Leaded Process Compatible:No; Output Voltage Max:1.3V; Peak Reflow Compatible (260 C):No; Supply Voltage Min:2.7V; Mounting Type:Surface Mount |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ST16C1551CJ28 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CJ28-F | 功能描述:UART 接口集成電路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C1551CP28 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CQ48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 16-BYTE FIFO |
| ST16C1551CQ48-F | 功能描述:UART 接口集成電路 UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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