<rt id="uramh"><delect id="uramh"></delect></rt>
        



    






  

    
    
    
  

  
  











 
 




 
 




    



參數(shù)資料









型號(hào)：
ST16C1551




廠商：
Exar Corporation




英文描述：
UART with 16-Byte FIFO(通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出）)




中文描述：
的UART具有16字節(jié)FIFO（通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出））




文件頁(yè)數(shù)：
18/32頁(yè)




文件大?。?/td>
418K




代理商：
ST16C1551








	

    
    

    

	
ST16C1550/51
18
Rev. 3.10
to minimize external software interaction. The Inter-
rupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the
ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are
acknowledged until the pending interrupt is serviced.
Whenever the interrupt status register is read, the
interrupt status is cleared. However it should be noted
that only the current pending interrupt is cleared by the
read. A lower level interrupt may be seen after reread-
ing the interrupt status bits. The Interrupt Source
Table 6 (below) shows the data values (bits 0-3) for the
four prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels:
Table 6, INTERRUPT SOURCE TABLE
Priority
Level
[ ISR BITS ]
Bit-3 Bit-2 Bit-1 Bit-0
Source of the interrupt
1
2
2
3
4
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents
may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (normal default condi-
tion)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2, 3, and 4 (See Interrupt
Source Table).
ISR BIT 4:
This bit represents the compliment (inversion) of the
TXRDY status when IER bit-5 is set to a logic 1.
Logic 0 = The UART transmitter is full.
Logic 1 = The UART transmitter is empty or is less than
empty in the FIFO mode. (normal default condition)
ISR BIT 5:
This bit represents the compliment (inversion) of the
RXRDY status when IER bit-5 is set to a logic 1.
Logic 0 = The UART receiver is empty. (normal default
condition)
Logic 1 = The UART receiver is not empty.
ISR BIT 6-7: (logic 0 or cleared is the default condition)
These bits are set to a logic 0 when the FIFOs are not
being used in the 16C450 mode. They are set to a logic
1 when the FIFOs are enabled in the ST16C550 mode.
Logic 0 = 16C450 mode.
Logic 1 = 16C550 mode.
Line Control Register (LCR)
The Line Control Register is used to specify the
asynchronous data communication format. The word
length, the number of stop bits, and the parity are
selected by writing the appropriate bits in this register.

    

    
    








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相關(guān)代理商/技術(shù)參數(shù)


參數(shù)描述






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ST16C1551CQ48-F
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