
8201, 8202, 8203, 8204 Acceleration Processor Data Sheet, DS-0157-05
Page 29
Exar Confidential
Table 2-1. Description of 820x Major Blocks
Block Name
Description
CC
Completion Controller
Receives the completion data from the PCIe Inbound Manager, and then
allocates the data to the proper Channel/PKP Manager according to the
tags.
CFG_REGS
Configuration Registers
Channel Manager
0/1
Channel Manager 0 and Channel Manager 1
Controls all command processing: fetching command structures and data
from host memory into the source buffer, transmitting results from the
result buffer to host memory.
CLK_RST_Gen
Clock and Reset Generation
Generates the clock and reset signals for all modules.
CPP
Command Pointer Ring Prefetch
Prefetches the command pointer from the command ring.
Encrypt Engine
Encryption Engine
Encrypts/Decrypts the data stream using the AES or 3DES algorithm.
GPIO
General Purpose IO
GZIP Engine
Compresses/Decompresses the data stream using the GZIP/Deflate
algorithms.
Hash Engine
Calculates the hash value or MAC value of the data stream.
LZS Engine
Compresses/Decompresses the data stream using the LZS or enhanced LZS
(eLZS) algorithm.
Pad Engine
Adds/Removes padding data from the data stream.
PCIe Core
PCI express end point controller
PCIe Serdes
PCI express physical layer
PIM
PCIe Inbound Manager
Receives the PCIe completion from the PCIe Core, and sends/receives
memory read/memory write to/from the PCIe Core.
PKP Engine
Public Key Processor Engine
The PKP engine consists of two pairs of public key processors.
PKP Manager
Controls instruction and operand data fetching from host memory to the
PKP engine, and transmits the calculated result from the PKP engine to host
memory.
POM
PCIe Outbound Manager
Sends the PCIe write data and read requests to the PCIe Core.
RNG
Random Number Generator
RRC
Read Request Controller
Arbitrates read requests from the CPP, Channel Manager 0, Channel
Manager 1 and PKP Manager, and sends read requests to the PCIe
Outbound Manager.