
8201, 8202, 8203, 8204 Acceleration Processor Data Sheet, DS-0157-05
Page 222
Exar Confidential
7.2.3
Power Management Capabilities Register
The Power Management Capabilities register is a 16-bit read-only register which provides
information on the capabilities of the function related to power management. The
information in this register is generally static and known at design time.
Offset
x‘0042’
Field Name
Bits
Type
820x
Value
Description
PME Support
15:11
RO
0x0B
PME Support.
Indicates the PM states supported by the
820x. A one in a bit indicates the 820x is
capable of sending a Power Management
Event (PME) message. A zero in a bit
indicates PME notification is not
supported in the respective PM state.
Bit
PM State
11
D0 (supported by 820x)
12
D1 (supported by 820x)
13
D2 (not supported by 820x)
14
D3hot (supported by 820x)
15
D3cold (not supported by 820x)
D2 Support
10
RO
0
D2 Support.
0 = D2 PM state not supported
D1 Support
9RO1
D1 Support.
1 = D1 PM state supported
Aux Current
8:6
RO
111
Aux Current.
The Aux_Current field reports the
3.3Vaux current requirements for the
820x. The 820x reports 375mA max.
Device-Specific
Initialization
5RO0
Device-Specific Initialization.
A one in this bit indicates that
immediately after entry into the D0
Uninitialized state, the 820x requires
additional configuration above and
beyond setup of its PCI configuration
Header registers before the Class driver
can use the 820x. Microsoft OSs do not
use this bit. Rather, the determination
and initialization is made by the Class
driver.
Reserved
4
RO
0
Reserved.
PME Clock
3
RO
0
The 820x does not use PME Clock.
Version Field
2:0
RO
0x3
Version Field.
This field indicates the version of the PCI
Bus PM Interface spec that the 820x
complies with.