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參數(shù)資料
| 型號： | ST10R172LT6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 6/68頁 |
| 文件大?。?/td> | 657K |
| 代理商： | ST10R172LT6 |
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ST10R172L - INTERRUPT AND TRAP FUNCTIONS
5
INTERRUPT AND TRAP FUNCTIONS
The architecture of the ST10R172L supports several mechanisms for fast and flexible
response to the service requests that can be generated from various sources, internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced, either by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In a standard interrupt service, program execution is suspended and a branch to the interrupt
service routine is performed. For a PEC service, just one cycle is ‘stolen’ from the current
CPU activity. A PEC service is a single, byte or word data transfer between any two memory
locations, with an additional increment of either the PEC source or the destination pointer. An
individual PEC transfer counter is decremented for each PEC service, except in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is performed
to the corresponding source-related vector location. PEC services are very well suited, for
example, to the transmission or reception of blocks of data. The ST10R172L has 8 PEC
channels, each of which offers fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag
and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related
register, each source can be programmed to one of sixteen interrupt priority levels. Once
having been accepted by the CPU, an interrupt service can only be interrupted by a higher
priority service request. For standard interrupt processing, each of the possible interrupt
sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs, feature programmable edge detection (rising edge,
falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
1
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