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參數(shù)資料
| 型號： | ST10R172LT6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 15/68頁 |
| 文件大小： | 657K |
| 代理商： | ST10R172LT6 |
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ST10R172L - SERIAL CHANNELS
10
SERIAL CHANNELS
Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP).
ASC0
A dedicated baud rate generator sets up standard baud rates without oscillator tuning. 3
separate interrupt vectors are provided for transmission, reception, and erroneous reception.
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start
bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism
to distinguish address from data bytes has been included (8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift
clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back
option is available for testing purposes.
A number of optional hardware error detection capabilities have been included to increase the
reliability of data transfers. A parity bit can be generated automatically on transmission, or
checked on reception. Framing error detection recognizes data frames with missing stop bits.
An overrun error is generated if the last character received was not read out of the receive
buffer register at the time the reception of a new character is complete.The table below lists
Figure 6 GPT2 block diagram
2n n=2...9
T5EUD
T5IN
CPU Clock
T6IN
T6EUD
T5
Mode
T6
Mode
GPT2 Timer T5
GPT2 Timer T6
U/D
Interrupt
Request
U/D
GPT2 CAPREL
T60TL
Toggle FF
T6OUT
CAPIN
Reload
Interrupt
Request
Capture
Clear
Interrupt
Request
1
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