參數(shù)資料
型號: ST10F269Z2Q3
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
封裝: 28 X 28 MM, PLASTIC, QFP-144
文件頁數(shù): 45/160頁
文件大?。?/td> 1541K
代理商: ST10F269Z2Q3
ST10F269
139/160
The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes fCPU to keep it
locked on fXTAL. The relative deviation of TCL is
the maximum when it is refered to one TCL
period. It decreases according to the formula and
to the Figure 68 given below. For N periods of TCL
the minimum value is computed using the
corresponding deviation DN:
where N = number of consecutive TCL periods
and 1
≤ N ≤ 40. So for a period of 3 TCL periods
(N = 3):
D3
=
4 - 3/15 = 3.8%
3TCLmin
=3TCLNOM x (1 - 3.8/100)
=3TCLNOM x 0.962
3TCLmin
=
36.075ns (at fCPU = 40MHz)
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train generation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible.
21.4.8 - External Clock Drive XTAL1
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125 °C
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz is the maximum input
frequency when using an external crystal oscillator. However, 40MHz can be applied with an external clock source.
2. The input clock signal must reach the defined levels VIL and VIH2.
TCL
MIN
TCL
NOM
1
D
N
100
-------------
×
=
D
N
4N 15
) %
[]
(
±
=
Figure 68 : Approximated Maximum PLL Jitter
Parameter
Symbol
fCPU = fXTAL
fCPU = fXTAL / 2
fCPU = fXTAL x F
F = 1.5/2,/2.5/3/4/5
Unit
min
max
min
max
min
max
Oscillator period
tOSC SR
25 1
12.5
40 x N
100 x N
ns
High time
t1
SR
10 2
5 2
10 2
–ns
Low time
t2
SR
10 2
5 2
10 2
–ns
Rise time
t3
SR
3 2
3 2
3 2
ns
Fall time
t4
SR
3 2
3 2
3 2
ns
32
16
8
4
2
±1
±2
±3
±4
Max.jitter [%]
N
This approximated formula is valid for
1
≤ N ≤ 40 and 10MHz ≤ f
CPU ≤ 40MHz.
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