參數(shù)資料
型號(hào): ST10F269Z2Q3
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
封裝: 28 X 28 MM, PLASTIC, QFP-144
文件頁數(shù): 19/160頁
文件大?。?/td> 1541K
代理商: ST10F269Z2Q3
ST10F269
115/160
EXICON (F1C0h / E0h
ESFR
Reset Value: 0000h
EXxIN inputs are normally sampled interrupt
inputs. However, the Power Down mode circuitry
uses them as level-sensitive inputs.
An EXxIN (x = 3...0) Interrupt Enable bit (bit
CCxIE in respective CCxIC register) need not be
set to bring the device out of Power Down mode.
An external RC circuit must be connected to RPD
pin, as shown in the Figure 61.
To exit Power Down mode with an external
interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40ns.
This signal enables the internal oscillator and PLL
circuitry, and also turns on the weak pull-down
(see Figure 62).
The discharge of the external capacitor provides a
delay that allows the oscillator and PLL circuits to
stabilize before the internal CPU and Peripheral
clocks are enabled. When the RPD voltage drops
below the threshold voltage (about 2.5V), the
Schmitt trigger clears Q2 flip-flop, thus enabling
the CPU and Peripheral clocks, and the device
resumes code execution.
If the Interrupt was enabled (bit CCxIE=’1’ in the
respective CCxIC register) before entering Power
Down mode, the device executes the interrupt
service routine, and then resumes execution after
the PWRDN intruction (see note below).
If the interrupt was disabled, the device executes
the instruction following PWRDN instruction, and
the Interrupt Request Flag (bit CCxIR in in the
respective CCxIC register) remains set until it is
cleared by software.
Note:
Due
to
the
internal
pipeline,
the
instruction
that
follows
the
PWRDN
intruction is executed before the CPU
performs a call of the interrupt service
routine when exiting power-down mode
15
14
13
12
11
10
9876543210
EXI7ES
EXI6ES
EXI5ES
EXI4ES
EXI3ES
EXI2ES
EXI1ES
EXI0ES
RW
EXIxES(x=7...0)
External Interrupt x Edge Selection Field (x=7...0)
0 0:
Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
0 1:
Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
1 0:
Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
1 1:
Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
Figure 61 : External R0C0 Circuit on RPD Pin For
Exiting Powerdown Mode with External Interrupt
RPD
VDD
C0
R0
220k
minimum
1
F Typical
ST10F269-Q3
+
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