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參數(shù)資料
| 型號(hào)： | SSTUG32865ET/S |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封裝： | 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 154K |
| 代理商： | SSTUG32865ET/S |
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SSTUG32865_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 August 2007
7 of 28
NXP Semiconductors
SSTUG32865
1.8 V DDR2-1G registered buffer with parity
[1]
If application does not require DCS2 and DCS3, it is allowed to connect H4 and K4 to VDD.
Program inputs
CSGATEEN
H1
1.8 V
LVCMOS
with weak
pull-up
Chip Select Gate Enable. When HIGH, the D0 to D21
inputs will be latched only when at least one Chip Select
input is LOW during the rising edge of the clock. When
LOW, the D0 to D21 inputs will be latched and redriven
on every rising edge of the clock.
SELDR
A2
LVCMOS
input
Selects output drive strength: ‘HIGH’ for normal drive,
‘LOW’ for high drive. This pin will default HIGH if left
open-circuit (built-in weak pull-up resistor).
Clock inputs
CK, CK
J1, K1
SSTL_18
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CK).
Miscellaneous inputs
MCL
U3, V2, V3
Must be connected to a logic LOW.
MCH
U5, V5
Must be connected to a logic HIGH.
RESET
L1
1.8 V
LVCMOS
with weak
pull-up
Asynchronous reset input. When LOW, it causes a reset
of the internal latches, thereby forcing the outputs LOW.
RESET also resets the PTYERR signal.
VREF
A1, V1
0.9 V
nominal
Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
VDDL
D4, E4, E6, F4, G4, K5, N4,
N5, P5, P6, R5, R6
Power supply voltage.
VDDR
E7, F8, F9, G8, G9, J8, J9,
L8, L9, N8, N9, P7, P8
Power supply voltage.
GND
D5, D8, D9, E5, E8, E9, F5,
G5, H5, H8, H9, J4, J5, K8,
K9, L4, L5, M4, M5, M8, M9,
P4, P9, R4, R7, R8, R9
Ground.
n.c.
A4, A5, B3, B4, B5, D6, D7,
V4
Ball present but not connected to die.
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTUG32866 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
| SSTUG32866EC/G | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
| SSTUG32866EC/G,518 | 功能描述:寄存器 1.8V REG RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTUG32866EC/G-T | 功能描述:寄存器 1.8V REG BUF/PARITY-DDR2-1G RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTUG32866EC/S | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer |
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