參數(shù)資料
型號(hào)： SSTUG32865ET/S
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 鎖存器
英文描述： SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160
封裝： 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160
文件頁(yè)數(shù)： 25/28頁(yè)
文件大小： 154K
代理商： SSTUG32865ET/S
SSTUG32865_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 16 August 2007
6 of 28
NXP Semiconductors
SSTUG32865
1.8 V DDR2-1G registered buffer with parity
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type
Description
Ungated inputs
DCKE0, DCKE1
U1, U2
SSTL_18
DRAM function pins not associated with Chip Select.
DODT0, DODT1
T2, T1
Chip Select gated inputs
D0 to D21
M1, B1, B2, C1, C2, D2, D1,
E1, E2, F2, M2, F1, G2, R1,
L2, H2, N2, N1, G1, P1, R2,
P2
SSTL_18
DRAM inputs, re-driven only when Chip Select is LOW.
Chip Select inputs
DCS0, DCS1,
DCS2, DCS3[1]
J2, K2, H4, K4
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will
be LOW when a valid address/command is present. The
register can be programmed to re-drive all D-inputs only
(CSGATEEN = HIGH) when at least one Chip Select
input is LOW. DCS2 and DCS3 are not re-driven and can
be left open-circuit to default HIGH by means of its
internal pull-up resistors.
Re-driven outputs
Q0A to Q21A
V11, F12, G12, V6, V9, H12,
L12, V8, V12, N12, M12,
P12, V7, V10, T12, R12,
E12, A12, A10, A9, D12, A8
SSTL_18
Outputs of the register, valid after the specied clock
count and immediately following a rising edge of the
clock.
Q0B to Q21B
U11, F11, G11, U6, U9,
H11, L11, U8, U12, N11,
M11, P11, U7, U10, T11,
R11, E11, A11, B10, B9,
D11, B8
QCS0A, QDS1A,
QCS0B, QCS1B
J12, K12, J11, K11
QCKE0A, QCKE1A,
QCKE0B, QCKE1B
A7, A6, B7, B6
QODT0A, QODT1A,
QODT0B, QODT1B
B12, C12, B11, C11
Parity input
PARIN
A3
SSTL_18
Parity input for the D0 to D21 inputs. Arrives one clock
cycle after the corresponding data input.
Parity error
PTYERR
U4
open-drain
When LOW, this output indicates that a parity error was
identied associated with the address and/or command
inputs. PTYERR will be active for two clock cycles, and
delayed by an additional clock cycle for compatibility with
nal parity out timing on the industry-standard DDR2
register with parity (in JEDEC denition).
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SSTUG32866EC/G 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/G,518 功能描述:寄存器 1.8V REG RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTUG32866EC/G-T 功能描述:寄存器 1.8V REG BUF/PARITY-DDR2-1G RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTUG32866EC/S 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
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