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參數資料
| 型號： | SSTUA32866EC/G,557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| 封裝： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件頁數： | 27/28頁 |
| 文件大小： | 153K |
| 代理商： | SSTUA32866EC/G,557 |
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SSTUA32866_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
8 of 28
NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 congurable registered buffer with parity
cascaded to the PAR_IN of the second register. The QERR output of the rst register is
left oating and the valid error information is latched on the QERR output of the second
register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,
and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (oating) data, clock and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and
all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid
logic HIGH or LOW level.
The device also supports low-power active operation by monitoring both system chip
select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states
when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn
and PPO outputs will function normally. The RESET input has priority over the DCS and
CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the
QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can
be hard-wired to ground, in which case, the setup time requirement for DCS would be the
same as for the other Dn data inputs. To control the low-power mode with DCS only, then
the CSR input should be pulled up to VDD through a pull-up resistor.
To ensure dened outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specied to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the Qn outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUA32866 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
相關PDF資料 |
PDF描述 |
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| SSTUAF32866BHLFT | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| SSTUAF32869AHLFT | 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150 |
| SSTUB32864EC/G | 32864 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUB32868ET/S | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| SSTUG32865ET/S | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SSTUA32S865 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications |
| SSTUA32S865BHLF | 功能描述:IC REGIST BUFF 25BIT DDR 160BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數:14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32S865BHLFT | 功能描述:IC REGIST BUFF 25BIT DDR 160BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數:14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| SSTUA32S865ET | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications |
| SSTUA32S865ET,518 | 功能描述:寄存器 1.8V 28BT REGBUFF/PAR-DDR2-667 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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