參數(shù)資料
型號(hào): SST89C58RC-40-C-QIF
廠商: Microchip Technology
文件頁(yè)數(shù): 66/88頁(yè)
文件大?。?/td> 0K
描述: IC MCU 8BIT FLASH 40WQFN
標(biāo)準(zhǔn)包裝: 81
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,I²C,SMBus,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-WFQFN 裸露焊盤
包裝: 管件
2011 Silicon Storage Technology, Inc.
DS25100A
12/11
69
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
Power-Saving Modes
The device provides two power saving modes of operation for applications where power consumption
is critical. The two modes are idle and power-down, see Table 26.
Idle Mode
Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program counter (PC) is
stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-
chip RAM and the special function registers hold their data during this mode.
The device exits idle mode through either a system interrupt or a hardware reset. Exiting idle mode via
system interrupt, the start of the interrupt clears the IDL bit and exits idle mode. After exit the Interrupt
Service Routine, the interrupted program resumes execution beginning at the instruction immediately
following the instruction which invoked the idle mode. A hardware reset starts the device similar to a
power-on reset.
Power-down Mode
The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode,
the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents
are retained during power-down, the minimum VDD level is 2.0V.
The device exits power-down mode through either an enabled external level sensitive interrupt or a
hardware reset. The start of the interrupt clears the PD bit and exits power-down. Holding the external
interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bring-
ing back high to complete the exit. Upon interrupt signal restored to logic VIH, the interrupt service rou-
tine program execution resumes beginning at the instruction immediately following the instruction
which invoked power-down mode. A hardware reset starts the device similar to power-on reset.
To exit properly out of power-down, the reset or external interrupt should not be executed before the
VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its nor-
mal operating level for the oscillator to restart and stabilize (normally less than 20 ms).
When the MCU is in power-down mode, a falling edge on the SDA pin of the SMBUS will wakeup the
MCU. Because the first byte may not be received by the SMBus correctly, the first START condition
may be missed because the oscillators will not start up.
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