參數(shù)資料
型號(hào): SST89C58RC-40-C-QIF
廠商: Microchip Technology
文件頁(yè)數(shù): 58/88頁(yè)
文件大小: 0K
描述: IC MCU 8BIT FLASH 40WQFN
標(biāo)準(zhǔn)包裝: 81
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,I²C,SMBus,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-WFQFN 裸露焊盤(pán)
包裝: 管件
2011 Silicon Storage Technology, Inc.
DS25100A
12/11
61
FlashFlex MCU
SST89C58RC
Data Sheet
A Microchip Technology Company
SMBus SCL High and Low Duty
SM0SCLH sets the SCL high duration and SM0SCLL sets the SCL low duration. The SM0SCLH and
SM0SCLL registers must be set to select the bit rate when the internal clock source for the SMBUS
SCL is selected. To select the internal serial clock source for the SM0CLL, set CRSEL = ‘0’ in the
SM0CON0 register.
Bit Rate = FPCLK /(4 x (SM0SCLH + SM0SCLL))
The registers can be set to different duty cycles for the SCL. While the values for the SM0SCLH and
SM0SCLL registers can be different, the value of the registers must keep the data rate in a data rate
range of 0-400 kHz, and ensure that the SCL high period is no less than 600ns and the low period is
no less than 1000ns. The values for both SM0SCLH and SM0SCLL should be at least three.
TIMER1 is used as the bit rate clock source when SRSEL is set. To generate the periodic pulse signal
that the SMBus uses to generate the bit rate clock, configure TIMER1 to mode 2. When TIMER1 is
used, the bit rate is calculated as:
Bit Rate = FPCLK / (96x (256 - TH1))
TH1 and TL1 are the high and low bytes counters for TIMER1. In mode 2, when TL1 counts to 0xFF,
the value of TH1 is automatically reloaded into TL1.
Table 24:Bit Rate Configuration1
1. SCL Bus Rise transition time (Tr) must be less than 300 ns.
SM0SCLH2 /
SM0SCLL3
2. SM0SCLH minimum value is 1400 ns/(4*CYCSYSCLK), but cannot be less than 3.
3. SM0SCLL minimum value is 1100 ns/(4*CYCSYSCLK), but cannot be less than 3.
CRSEL
Bit Rate4 (Kbit/s) at FPCLK
4. Baud rate setting must not exceed 400 Kbit per second.
6MHz
12MHz
33MHz
40MHz
6
250
-
8
0
188
375
-
15
0
100
200
-
25
0
60
120
330
400
40
0
38
75
197
250
50
0
30
60
165
200
100
0
15
30
83
100
150
0
102055
67
200
0
8
15
42
50
250
0
6
12
33
40
300
0
5
10
28
34
400
0
4
8
21
25
510
0
3
6
16
20
Bit Rate (TIMER15 in mode2)
5. If using TIMER1 as the baud rate clock source, TH1 must be 0-254 if the system clock is higher than 20 MHz. If the sys-
tem clock is lower than or equal to 20 MHz, TH1 can only be 0-255.
0.25-63Kbps
0.49-125Kbps
1.34-172Kbps
1.63-208Kbps
T0-0.25100
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