參數(shù)資料
型號: SST55LC100-45-C-BWE
元件分類: 存儲控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA84
封裝: ROHS COMPLIANT, MO-210, TFBGA-84
文件頁數(shù): 66/80頁
文件大?。?/td> 758K
代理商: SST55LC100-45-C-BWE
Advance Information
CompactFlash Card Controller
SST55LC100
2005 Silicon Storage Technology, Inc.
S71298-00-000
10/05
69
10.2.5 I/O Input (Read) Timing Specification
Note: The maximum load on -INPACK and IOIS16# is 1 LSTTL with 50pF total load.
FIGURE
10-6: I/O READ TIMING DIAGRAM
TABLE 10-11: I/O READ TIMING
Item
Symbol
IEEE Symbol
Min1
1. All AC specifications are guaranteed by design.
Units
Data Delay after IORD
td(IORD)
tlGLQV
100
ns
Data Hold following IORD
th(IORD)
tlGHQX
0
ns
IORD Width Time
tw(IORD)
tlGLIGH
165
ns
Address Setup before IORD
tsuA(IORD)
tAVIGL
70
ns
Address Hold following IORD
thA(IORD)
tlGHAX
20
ns
CE Setup before IORD
tsuCE(IORD)
tELIGL
5
ns
CE Hold following IORD
thCE(IORD)
tlGHEH
20
ns
REG Setup before IORD
tsuREG(IORD)
tRGLIGL
5
ns
REG Hold following IORD
thREG(IORD)
tlGHRGH
0
ns
INPACK Delay Falling from IORD
tdfINPACK(IORD)
tlGLIAL
0
45
ns
INPACK Delay Rising from IORD
tdrINPACK(IORD)
tlGHIAH
45
ns
IOIS16 Delay Falling from Address
tdfIOIS16(ADR)
tAVISL
35
ns
IOIS16 Delay Rising from Address
tdrIOIS16(ADR)
tAVISH
35
ns
T10-11.0 1298
1298 F07.0
REG#
tdrINPACK(IORD)
tdfINPACK(IORD)
tdrIOIS16(ADR)
thA(IORD)
thREG(IORD)
thCE(IORD)
td(IORD)
th(IORD)
DOUT
tw(IORD)
tsuA(IORD)
tsuREG(IORD)
tsuCE(IORD)
An
CE#
IORD#
INPACK#
IOIS16#
DOUT
tdfIOIS16(ADR)
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