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參數(shù)資料
| 型號： | SPAK56F807VF80 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 80 MHz, OTHER DSP, PBGA160 |
| 封裝： | MOLD ARRAY PROCESS, BGA-160 |
| 文件頁數(shù)： | 8/48頁 |
| 文件大小： | 853K |
| 代理商： | SPAK56F807VF80 |
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16
DSP56F807 Preliminary Technical Data
MOTOROLA
Part 3 Specifications
3.1 General Characteristics
The DSP56F807 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such sytems, a bus may carry both 3.3V and 5V-
compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
± 10%
during normal operation without causing damage). This 5V tolerant capability therefore offers the power
savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 20 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The DSP56F807 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum rated voltages to this high-
impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
Table 20. Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
Supply voltage
VDD
VSS – 0.3
VSS + 4.0
V
All other input voltages, excluding Analog inputs
VIN
VSS – 0.3
VSS + 5.5V
V
Analog inputs, ANA0-7 and VREF
VIN
VSSA– 0.3
VDDA+ 0.3
V
Analog inputs EXTAL and XTAL
VIN
VSSA– 0.3
VSSA+ 3.0
V
Current drain per pin excluding VDD, VSS, PWM
outputs, TCS, VPP, VDDA, VSSA
I—
10
mA
Current drain per pin for PWM outputs
I
—
20
mA
Junction temperature
TJ
—150
°C
Storage temperature range
TSTG
-55
150
°C
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