參數(shù)資料
型號: SPAK56F807VF80
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝: MOLD ARRAY PROCESS, BGA-160
文件頁數(shù): 18/48頁
文件大?。?/td> 853K
代理商: SPAK56F807VF80
External Clock Operation
MOTOROLA
DSP56F807 Preliminary Technical Data
25
Figure 12. External Clock Timing
Table 28. External Clock Operation Timing Requirements5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)1
1.
See Figure 11 for details on using the recommended connection of an external clock driver.
fosc
08
80
MHz
Clock Pulse Width2, 5
2.
The high or low pulse width must be no smaller than 6.25 ns or the chip will not function.
tPW
6.25
——
ns
External clock input rise time3, 5
3.
External clock input rise time is measured from 10% to 90%.
trise
——
3
ns
External clock input fall time4, 5
4.
External clock input fall time is measured from 90% to 10%.
5.
Parameters listed are guaranteed by design.
tfall
——
3
ns
Table 29. PLL Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL1
1.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8 MHz input crystal.2.
fosc
48
8
MHz
PLL output frequency2 (Fout/2)
2.
ZCLK may not exceed 80 MHz. For additional information on ZCLK and Fout/2, please refer to the OCCS chapter
in the User Manual.
fop
40
—110
MHz
PLL stabilization time3 0o to +85oC
3.
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
tplls
—1
10
ms
PLL stabilization time3 -40o to 0oC
tplls
100
200
ms
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10%
tPW
tfall
trise
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