參數(shù)資料
型號: SPAK56F807VF80
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 80 MHz, OTHER DSP, PBGA160
封裝: MOLD ARRAY PROCESS, BGA-160
文件頁數(shù): 21/48頁
文件大?。?/td> 853K
代理商: SPAK56F807VF80
28
DSP56F807 Preliminary Technical Data
MOTOROLA
Figure 14. Asynchronous Reset Timing
Figure 15. External Interrupt Timing (Negative-Edge-Sensitive)
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
275,000T
12T
ns
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
275,000T
12T
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
275,000T
12T
ns
1.
In the formulas, T = clock cycle. For an operating frequency of 80 MHz, T = 12.5 ns.
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
3.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.
This is not the minimum required so that the IRQA interrupt is accepted.
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
Table 31. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,5 (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL 50 pF
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
See
Figure
First Fetch
tRA
tRAZ
tRDA
A0–A15,
D0–D15
PS, DS,
RD, WR
RESET
First Fetch
IRQA,
IRQB
tIRW
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