- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98136 > SNJ54BCT8374AJT (TEXAS INSTRUMENTS INC) BCT/FBT SERIES, 8-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, CDIP24 PDF資料下載
參數(shù)資料
| 型號： | SNJ54BCT8374AJT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | BCT/FBT SERIES, 8-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, CDIP24 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-24 |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 434K |
| 代理商： | SNJ54BCT8374AJT |
SN54BCT8374A, SN74BCT8374A
SCAN TEST DEVICES
WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCBS045E JUNE 1990 REVISED JULY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’BCT8374A, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.
Run-Test / Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.
The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register may capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SNJ54F02FK | F/FAST SERIES, QUAD 2-INPUT NOR GATE, CQCC20 |
| SNJ54F153FKR | F/FAST SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CQCC20 |
| SN74F153DE4 | F/FAST SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| SNJ54F244J | F/FAST SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| SNJ54F245FKR | F/FAST SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CQCC20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SNJ54CBT16244WD | 制造商:Texas Instruments 功能描述:Bus Switch 4-Element CMOS 16-IN 48-Pin CFPAK Tube |
| SNJ54CBT3383JT | 制造商:Texas Instruments 功能描述:Bus Exchange Switch 1-Element 5-CH 24-Pin CDIP Tube |
| SNJ54CBTD3384JT | 制造商:Texas Instruments 功能描述:Bus Switch 2-Element CMOS 10-IN 24-Pin CDIP Tube 制造商:Texas Instruments 功能描述:5962-9752701QLA - Rail/Tube |
| SNJ54CBTD3384W | 制造商:Texas Instruments 功能描述:5962-9752701QKA |
| SNJ54F00FK | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。