
SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
13
instruction register opcode description
The instruction register opcodes are shown in Table 4. The following descriptions detail the operation of each
instruction.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The
boundary-scan register is selected in the scan path. Data appearing at the device input pins is captured in the
input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data
scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data scanned into the
output BSCs is applied to the device output pins. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The
boundary-scan register is selected in the scan path. Data appearing at the device input pins is captured in the
input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The
device operates in the normal mode.
control boundary to high impedance
This instruction conforms to the IEEE P1149.1A HIGHZ instruction. The bypass register is selected in the scan
path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified
test mode in which all device I/O pins are placed in the high-impedance state, the device input pins remain
operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE P1149.1A CLAMP instruction. The bypass register is selected in the scan
path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input BSCs is applied
to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device output pins. The
device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the boundary-control register
is executed during Run-Test/Idle. The five test operations decoded by the boundary-control register are: sample
inputs/toggle outputs (TOPSIP), pseudo-random pattern generation (PRPG), parallel signature analysis (PSA),
simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up (PSA/COUNT).
boundary read
The boundary-scan register is selected in the scan path. The value in the boundary-scan register remains
unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation.
boundary self test
The boundary-scan register is selected in the scan path. All BSCs capture the inverse of their current values
during Capture-DR. In this way, the contents of the shadow latches can be read out to verify the integrity of both
shift register and shadow latch elements of the boundary-scan register. The device operates in the normal
mode.