參數(shù)資料
型號: SN74ABT18245ADGG
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝: PLASTIC, TSSOP-56
文件頁數(shù): 29/31頁
文件大?。?/td> 438K
代理商: SN74ABT18245ADGG
SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS
SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO. On the first
falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level
present in the least significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such updates occur
on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the ’ABT18245A, the
status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On
the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the
logic level present in the least significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of
data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR
state.
相關(guān)PDF資料
PDF描述
SN74ABT18502PMR ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64
SN74ABT18502PM ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64
SN74ABT18504PMRG4 ABT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64
SN74ABT18640DGGR ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56
SN74ABT18640DLR ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74ABT18245ADGGR 功能描述:特定功能邏輯 Scan Test Device RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
SN74ABT18245ADL 功能描述:特定功能邏輯 Scan Test Device RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
SN74ABT18245ADLG4 功能描述:特定功能邏輯 Scan Test Device w/18-Bit Bus Trnscvr RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
SN74ABT18245ADLR 功能描述:特定功能邏輯 Scan Test Device RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube
SN74ABT18245ADLRG4 功能描述:特定功能邏輯 Scan Test Device RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube