- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98089 > SN54LVTH18502AHV (TEXAS INSTRUMENTS INC) LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 PDF資料下載
參數(shù)資料
| 型號： | SN54LVTH18502AHV |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 31/38頁 |
| 文件大?。?/td> | 556K |
| 代理商： | SN54LVTH18502AHV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
Product Folder: SN54LVTH18502A, 3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of
CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA\, LEBA, and CLKBA
inputs.
In the test mode, the normal operation of the SCOPETM universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test
circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test
circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are
synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of 'LVTH182502A, which are designed to source or sink up to 12 mA, include 25-
series resistors to reduce overshoot and undershoot.
The SN54LVTH18502A and SN54LVTH182502A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH18502A and SN74LVTH182502A are characterized for
operation from -40°C to 85°C.
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA\, LEBA, and CLKBA.
Output level before the indicated steady-state input conditions are established
TECHNICAL DOCUMENTS
To view the following documents, Acrobat Reader 4.0 is required.
To download a document to your hard drive, right-click on the link and choose 'Save'.
DATASHEET
APPLICATION NOTES
View Application Notes for Digital Logic
q
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) (SZZA029B - Updated: 05/22/2002)
q
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) (SCBA012A - Updated: 08/01/1997)
q
Evaluation of Nickel/Palladium/Gold-Finished Surface-Mount Integrated Circuits (SZZA026 - Updated: 06/20/2001)
q
q
q
q
q
q
q
q
q
q
Understanding and Interpreting Texas Instruments Standard-Logic Products Data Sh (Rev. A) (SZZA036A - Updated: 02/27/2003)
MORE LITERATURE
q
q
q
q
q
q
Overview of IEEE Std 91-1984, Explanation of Logic Symbols Training Booklet (Rev. A) (SDYZ001A, 138 KB - Updated: 07/01/1996)
q
file:///E|/042120003_HTML/sn54lvth18502a.html (2 of 3) [24-Apr-03 3:02:20 PM]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LVTH182512HKC | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CDFP64 |
| SN54LVTH182516HKC | LVT SERIES, 18-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CDFP64 |
| SNJ54LVTH18516HKC | LVT SERIES, 18-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CDFP64 |
| SNJ54LVTH182516HKC | LVT SERIES, 18-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CDFP64 |
| SN54LVTH182646AHV | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54S00J | 制造商:Texas Instruments 功能描述:NAND Gate 4-Element 2-IN Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S00W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S02J | 制造商:Texas Instruments 功能描述: |
| SN54S03J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:2-INPUT NAND GATE (OC) - Rail/Tube |
| SN54S04J | 制造商:Texas Instruments 功能描述:Inverter 6-Element Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:INVERTER 6-ELEM BIPOLAR 14CDIP - Rail/Tube 制造商:Texas Instruments 功能描述:HEX INVERTER *NIC* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。