- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98083 > SMJ320C26FJ (TEXAS INSTRUMENTS INC) 16-BIT, 40 MHz, OTHER DSP, CQCC68 PDF資料下載
參數(shù)資料
| 型號： | SMJ320C26FJ |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 40 MHz, OTHER DSP, CQCC68 |
| 封裝： | CERAMIC, LCC-68 |
| 文件頁數(shù)： | 23/40頁 |
| 文件大小： | 577K |
| 代理商： | SMJ320C26FJ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PIN NOMENCLATURE
NAME
I/O/Z
DEFINITION
VCC
I
5-V supply pins.
VSS
I
Ground pins.
X1
O
Output from internal oscillator for crystal.
X2/CLKIN
I
Input to internal oscillator from crystal or external clock.
CLKOUT1
O
Master clock output (crystal or CLKIN frequency/4).
CLKOUT2
O
A second clock output signal.
D15–D0
I/O/Z
16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data and I/O spaces.
A15–A0
O/Z
16-bit address bus A15 (MSB) through A0 (LSB).
PS, DS, IS
O/Z
Program, data and I/O space select signals.
R/W
O/Z
Read/write signal.
STRB
O/Z
Strobe signal.
RS
I
Reset input.
INT2, INT1, INT0
I
External user interrupt inputs.
MP/MC
I
Microprocessor/microcomputer mode select pin.
MSC
O
Microstate complete signal.
IACK
O
Interrupt acknowledge signal.
READY
I
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction
is complete.
BR
O
Bus request signal. Asserted when the SMJ320C26 requires access to an external global data memory space.
XF
O
External flag output (latched software – programmable signal).
HOLD
I
Hold input. When asserted, SMJ320C26 goes into an idle mode and places the data address and control lines
in the high-impedance state.
HOLDA
O
Hold acknowledge signal.
SYNC
I
Synchronization input.
BIO
I
Branch control input. Polled by BIOZ instruction.
DR
I
Serial data receive input.
CLKR
I
Clock input for serial port receiver.
FSR
I
Frame synchronization pulse for receive input.
DX
O/Z
Serial data transmit output.
CLKX
I
Clock input for serial port transmitter.
FSX
I/O/Z
Frame synchronization pulse for transmit. May be configured as either an input or an output.
I/O/Z denotes input/output/high-impedance state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SMJ320C31KGDM40B | 32-BIT, 40 MHz, OTHER DSP, UUC132 |
| SMJ320C40KGDS50C | 32-BIT, 50 MHz, OTHER DSP, UUC325 |
| SMJ320C40TABM40/10 | 32-BIT, 40 MHz, OTHER DSP, UUC325 |
| SM320C40TABS60/10 | 32-BIT, 60 MHz, OTHER DSP, UUC325 |
| SMJ320C6201BGLPW20 | 32-BIT, 200 MHz, OTHER DSP, CBGA429 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C30 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
| SMJ320C30-40 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
| SMJ320C30-50 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
| SMJ320C30GB | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
| SMJ320C30GBM40 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。