參數(shù)資料
型號(hào)： SMJ320C26FJ
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 16-BIT, 40 MHz, OTHER DSP, CQCC68
封裝： CERAMIC, LCC-68
文件頁(yè)數(shù)： 19/40頁(yè)
文件大?。?/td> 577K
代理商： SMJ320C26FJ
SMJ320C26
DIGITAL SIGNAL PROCESSOR
SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SERIAL PORT TIMING
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
MIN
MAX
UNIT
td(CH-DX)
DX valid after CLKX rising edge (see Note 8)
80
ns
td(FL-DX)
DX valid after FSX falling edge (TXM = 0) (see Note 8)
45
ns
td(CH-FS)
FSX valid after CLKX rising edge (TXM = 1)
45
ns
timing requirements over recommended operating conditions (see Note 1)
MIN
MAX
UNIT
fsx
Serial port frequency
1.25
5,000
kHz
tc(SCK)
Serial port clock (CLKX/CLKR) cycle time
200
800,000
ns
tw(SCK)
Serial port clock (CLKX/CLKR) low pulse duration (see Note 9)
80
ns
tw(SCK)
Serial port clock (CLKX/CLKR) high pulse duration (see Note 9)
80
ns
tsu(FS)
FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)
18
ns
th(FS)
FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)
20
ns
tsu(DR)
DR setup time before CLKR falling edge
10
ns
th(DR)
DR hold time after CLKR falling edge
20
ns
NOTES:
1. Q = 1/4tc(C)
8. The last occurrence of FSX falling and CLKX rising.
9. The duty cycle of the serial port clock must be within 40–60%. Serial port clock (CLKX/CLKR) rise and fall times must be less than
25 ns.
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