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參數(shù)資料
| 型號： | SME5434PCI-480 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 480 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁數(shù)： | 32/34頁 |
| 文件大小： | 418K |
| 代理商： | SME5434PCI-480 |
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7
360/440/480MHz CPU; 0.25 to 2 MB L2 cache, UPA64S, 66MHz PCI
UltraSPARC-IIi CPU Module
March 1999
Sun Microsystems, Inc
SME5431PCI-360
SME5434PCI-440
SME5434PCI-480
Preliminary
TECHNICAL CAPABILITIES
One of the features of the UltraSPARC-IIi CPU is the superior performance of its integrated I/O, DRAM and
UPA64S interfaces.
.
Note: DRAM bandwidth is 25%–33% greater than these numbers since there is an initial DRAM read of
the data locations that is used for store operations.
SPEC Performance
Estimated Performance
Conditions
360 MHz CPU
SPECint95
15.1
using 50 ns DIMMs; 2-2-2 mode, 0.25 megabyte L2 cache
SPECfp95
18.0
440 MHz CPU
SPECint95
18.7
50 ns DIMMs; 2-2 mode, 2 megabyte L2 cache
SPECfp95
21.1
480 MHz CPU
SPECint95
20.2
50 ns DIMMs; 2-2 mode 2 megabyte L2 cache
SPECfp95
22.5
Memory Performance
Parameter
Specication (Estimated)
Unit
360 MHz CPU [1]
440 MHz CPU [2]
480 MHz CPU [2]
Maximum L2- cache read bandwidth
1.44
1.76
1.92
GB/s
Maximum L2- cache write bandwidth
1.44
1.76
1.92
GB/s
Maximum DRAM random read bandwidth
388
440
465
MB/s
Maximum DRAM random write bandwidth
388
440
465
MB/s
Maximum same page read bandwidth
480
586
639
MB/s
Memcopy, from DRAM to DRAM
351
410
436
MB/s
Memcopy, from DRAM to UPA64S bus
524
552
591
MB/s
FP Vector
Specication
Sustained Performance (Estimated)
Unit
360 MHz CPU [1]
1. 0.25 MB L2 cache using 50 ns DIMMs
440 MHz CPU [2]
2. 2.0 MB L2 cache; using 50 ns DIMMs
480 MHz CPU [3]
3. 2.0 MB L2 cache; using 50 ns DIMMs
STREAM Copy (compiled)
218
242
254
MB/s
STREAM Scale (compiled)
218
243
254
MB/s
STREAM Add (compiled)
248
274
286
MB/s
STREAM Triad (compiled)
248
274
286
MB/s
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