參數(shù)資料
型號(hào)： SME5434PCI-480
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 480 MHz, RISC PROCESSOR, XMA
封裝： 130 X 100 MM, 45 MM HEIGHT MODULE
文件頁(yè)數(shù)： 30/34頁(yè)
文件大?。?/td> 418K
代理商： SME5434PCI-480
5
360/440/480MHz CPU; 0.25 to 2 MB L2 cache, UPA64S, 66MHz PCI
UltraSPARC-IIi CPU Module
March 1999
Sun Microsystems, Inc
SME5431PCI-360
SME5434PCI-440
SME5434PCI-480
Preliminary
The 360 MHz UltraSPARC-IIi CPU Module runs its L2-cache SRAM interfaces in 2-2-2 register-register mode,
which means that it takes two processor clocks to send the address and access the SRAM array, two clocks to
access the data and two clocks to return the data. The 2-2-2 mode has a six cycle pin-to-pin latency.
The external
-cache SRAMs are housed in 119-pin, plastic, 50-mil, BGA packages, measuring 22 mm by 14
mm.
Clock Generation
Motorola LVPECL and HSTL devices are used to generate clocks for the processor, the SRAMs, and the
UPA64S interface. The processor doubles the input pin clock frequency to generate the CPU pipeline
frequency.
System Functions
The following list gives system functions, with their corresponding CPU-derived clock rates.
FFB/UPA 64S interface: 64-bit; 1/4 CPU pipeline frequency
On-module L2- cache tag SRAM: 16-bit + 2 parity; runs at 1/2 CPU pipeline frequency
On-module L2- cache data SRAMs: 64-bit + 8 parity; runs at 1/2 CPU pipeline frequency
DRAM data interface: 64 + 8-ECC bits; congured for external multiplexing to 128 + 16-ECC bits at the
DRAM interface; programmed by software at an equivalent of 1/4 or 1/5 of the CPU pipeline frequency
The PCI bus clock is generated by the system board and is an input to the module. It is asynchronous with
respect to the CPU clock. The PCI bus is 32 bits wide and can run at a maximum frequency of 66 MHz.
External Connector Pin Assignments
The module connector pins include round and at blade pins for signals and power respectively. The pin
assignments are shown in Figure 2. Pin lists, by location and alphabetically by signal name, are presented at
the back of this datasheet.
This module requires two supply voltages, both driven by external system supplies on the inner pins (blades)
of the connector.
VDD, nominally 3.3 V, powers the CPU I/O and the SRAM core.
VDD_CORE, nominally 1.9 V, supplies the core of the processor chip and the SRAM I/O on the module.
The pin locations are shown in Figure 2.
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