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參數(shù)資料
| 型號(hào)： | SMD1108 |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device |
| 中文描述： | 8通道自動(dòng)監(jiān)控ADC的在系統(tǒng)可編程模擬（ISPA）設(shè)備 |
| 文件頁數(shù)： | 5/29頁 |
| 文件大?。?/td> | 734K |
| 代理商： | SMD1108 |
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5
2052 2.0 10/05/01
SMD1108
Preliminary
SUMMIT MICROELECTRONICS, Inc.
V
CC0
/CH4 – V
CC3
/CH7 (38, 39, 40, 41)
These 4 inputs are used as the voltage monitor inputs and
the voltage supply for the SMD1108. Internally they are
diode ORed and the input with the highest voltage poten-
tial will be the default supply voltage. For proper device
operation at least one of the inputs must be at 2.7V or
higher. V
CC0
/CH4 to V
CC3
/CH7 are also inputs to four
programmable comparators. The under-voltage and
over-voltage threshold voltage of each comparator is
programmable.
V
REFIN
(29)
A reference voltage for the ADC. The user can select
either the VREFIN as the ADC reference or use the default
internal reference voltage.
V
REFOUT
(20)
The internally generated reference voltage. It is program-
mable and can supply either 2.048V or 2.500V.
AGND, DGND
,
PGND, GND (19, 18, 17, 8)
These are the analog, digital, package, and common
ground inputs, respectively. They should all be tied to the
same ground plane.
AUXV
CC
(42)
AUXV
CC
should be isolated from the system power
supplies and tied to ground through capacitor C
B/U
. During
normal device operation C
B/U
will be charged by the
system supplies through the SMD1108. If system power
is lost the charge on C
B/U
will be used to store the status
of the monitor inputs. A 10μF tantalum capacitor should
be used for C
B/U
.
In the system environment AUXVcc could also be con-
nected to the front of the card (along with SDA and SCL
and GND) so that power could be applied to the SMD1108
to read the contents of the NV status registers.
A0, A1 and A2
(43, 44, 45)
Address inputs. When addressing the SMD1108 either as
a memory or an analog channel (or configuration register)
the address inputs distinguish which one of eight possible
devices sharing the common bus is being addressed.
CE# (22)
A control mechanism for the 2-wire interface. The true
state polarity is programmable. When driven true the
interface is active and communications channels are
open. When it is driven false all communications via the
bus are disabled.
PIN DESCRIPTIONS
SDA (46)
Serial data input/output pin. It should be tied to V
CC
through a 10k
pull-up resistor.
SCL (47)
Serial clock input pin. It should be tied to V
CC
through a
10k
pull-up resistor.
CH0 to CH3 (33, 32, 31, 30)
The analog channel inputs. These inputs are monitored
solely through the use of the ADC.
OC0 to OC3 (37, 36, 35, 34)
Over-current sense inputs. They are paired with VCC0/
CH4 to VCC3/CH7, respectively, and have a fixed 50mV
offset with respect to their corresponding channel input.
MR# (5)
An active low manual reset input. When MR# is driven low
the reset output will immediately be driven low. MR# is not
maskable and will always generate a reset sequence. The
duration of the RST# pulse will be equal to the length of the
MR# input pulse plus the programmed reset time-out
period value.
WD_EN# (3)
The enable input for both the Watchdog and the Longdog.
It must be driven low to enable the operation of their
timers. This can provide a convenient mechanism during
“debug of code” or during a “power-on configuration”
sequence.
WLDI (48)
The Watchdog timer interrupt input. A low to high
transition on WDI will reset the Watchdog and Longdog
timers. If the timer is not reset within the programmed
period of time the SMD1108 will activate the WDO# output
first and then the LDO# output.
RST# (15)
An active low open drain output. It will be driven low by
the combination of VCC0/CH4 to VCC3/CH7 being at
levels below their programmed settings and/or MR# being
driven low. RST# will stay low for the duration of the fault
condition or the MR# low input and remain low for the
duration of t
PURST
after the removal of the fault condition
or MR# returning high.
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