參數(shù)資料
型號： SMD1108
廠商： Summit Microelectronics, Inc.
英文描述： 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device
中文描述： 8通道自動監(jiān)控ADC的在系統(tǒng)可編程模擬（ISPA）設(shè)備
文件頁數(shù)： 10/29頁
文件大?。?/td> 734K
代理商： SMD1108
10
SMD1108
2052 2.0 10/05/01
Preliminary
SUMMIT MICROELECTRONICS, Inc.
The SMD1108 automatically increments the address for
subsequent data words. After the receipt of each word the
low order address bits are internally incremented by one.
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generating the Stop condition, the address counter will
rollover, and the previously written data will be overwrit-
ten. As with the byte Write operation all inputs are
disabled during the internal write cycle. Refer to Figure
2 for the address, Acknowledge, and data transfer se-
quence.
Acknowledge Polling
When the SMD1108 is performing an internal Write
operation it will ignore any new Start conditions. Since the
device will only return an acknowledge after it accepts the
Start, the part can be continuously queried until an
acknowledge is issued, indicating that the internal Write
cycle is complete. See the flow diagram (Figure 3) for the
proper sequence of operations for polling.
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to 1. There are two different Read
options: (1) Current Address Byte Read; or (2) Random
Address Byte Read
Current Address Read
The SMD1108 contains an internal address counter which
maintains the address of the last word accessed, incre-
Figure 2. Address, Acknowledge and Data Transfer Sequence
Figure 3. Polling Sequence
A
C
K
A
2
A
1
A
0
R
/
W
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
D
7
D
6
D
1
D
0
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
S
T
A
R
T
A
C
K
A
2
A
1
A
0
R
/
W
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
D
7
D
6
D
1
D
0
A
C
K
S
T
O
P
Typical Write Operation
Typical Read Operation
Master
SDA
Slave
Master
SDA
Slave
2052 Fig02 2.0
N
A
C
K
Next
Operation
a Write
ACK
Returned
Issue
Address
Proceed
With
Write
Await
Next
Command
Issue Stop
Issue Slave
Address and
R/W = 0
Issue Stop
Write Cycle
In Progress
Yes
No
Issue Start
2052 Fig03
Yes
No
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