參數(shù)資料
型號(hào)： SMD1108
廠商： Summit Microelectronics, Inc.
英文描述： 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device
中文描述： 8通道自動(dòng)監(jiān)控ADC的在系統(tǒng)可編程模擬（ISPA）設(shè)備
文件頁(yè)數(shù)： 27/29頁(yè)
文件大?。?/td> 734K
代理商： SMD1108
27
2052 2.0 10/05/01
SMD1108
Preliminary
SUMMIT MICROELECTRONICS, Inc.
Each Channel has two 10-bit threshold registers, one for
the high threshold and one for the low threshold. The
channels can be set up to measure the signals as shown
in Figure 11.
If the ADC output falls into the Alert region the SMD1108
can be programmed to change any of the following
signals: HEALTHY#, FAULT#, FAULT_IRQ#, and
LIM_IRQ#.
In addition, the SMB Alert Output will become active.
SMB
ALERT
is a special interrupt which can be used to
signal to the processor that a fault has occurred. The
processor will issue a special SMB message on the serial
data bus, all devices on the serial data bus will listen to
the command, and the device responsible for the SMB
Alert will identify its own address, as defined by the
address pins (see serial data bus section). Note the
processor must take the SMD1108 out of Automonitor
mode prior to sending the SMB message.
General Purpose Outputs
There are 4 General Purpose Outputs which can be
controlled via the serial data bus. Each signal can be
controlled independently. These are open collector
outputs, which are capable of sinking 5mA, suitable for
driving low current LEDs. The Serial Data Bus must be
active in order to control the GPO’s (
i.e.
, not in Automoni-
tor mode).
Nonvolatile Memory
In addition to programming registers the SMD1108 con-
tains 1k bits of NV Memory, which can be accessed by
a host processor using the Serial Data Bus. The NV
memory looks like a conventional Serial EEPROM, using
Serial Data Bus address 1010. The memory is organized
as 128
×
8 bits.
Processor Supervisor Functions
Integrated into the SMD1108 are the typical functions
found around a host microprocessor/microcontroller.
These include reset controller, manual reset function, and
a two stage watchdog timer. The RST# output signal is
a function of the following inputs: Voltage Thresholds in
CH4 through CH7 (can be overridden by UV_OVRD
signal), the Manual Reset Input (MR#), and an Alarm from
the Instant Action Block.
For each channel, which has an active UV Threshold, all
channels must have a voltage above their pre-pro-
grammed UV threshold. The MR# input is intended for a
front panel reset switch. This input is debounced inter-
nally and will produce a rest pulse width according to the
values programmed in using the GUI. A two-stage timer
is provided: the Watchdog and Longdog timers. Each
timer has its own respective output (WDO and LDO), but
both are triggered from a common input signal (WLDI).
Normally the shorter time is programmed in the Watchdog
timer. The Watchdog timer and Longdog Timer values are
set in the GUI.
Serial Data Bus Interface
The SMD1108 has a serial data bus interface using clock
(SCL) and data (SDA) lines. See the Serial Interface
section for timing requirements. There are also three
Address pins — A2, A1, A0 — which are used to select
the device bus address. This allows 8 unique addresses
on the bus. If the address range needs further expansion
a separate CE# pin is provided. As the CE# pin enables
all data bus communication with the device it must be set
to the correct level for access.
The first 4 bits of the 8 bit data sent to the SMD1108 are
used to access various internal functions:
0001
BIN
— SMB Alert Protocol,
1001
BIN
— Limit Register Access (CH0 to CH3),
1010
BIN
— Memory Access,
1011
BIN
— Configuration Register Access.
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