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參數(shù)資料
| 型號： | SM320MCM42CHFNM40 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, CQFP408 |
| 封裝： | TIE-BAR, CERAMIC, QFP-408 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 358K |
| 代理商： | SM320MCM42CHFNM40 |
SMJ320MCM42C, SMJ320MCM42D
DUAL SMJ320C40 MULTICHIP MODULE
SGKS001D – JULY 1997 – REVISED OCTOBER 2001
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
application note
For all MCM42x product manufactured prior to August 1, 2001 (i.e., date codes older than 0131), users should
reference the application note on page 10 of SGKS001B (July 1997 - Revised February 2000) for proper
memory function.
The following application note applies to MCM42x product manufactured after August 1, 2001 (i.e., date codes
newer than 0131). Changes to this application note from the previous data sheet revision impact the MCM42C
only. Note: The information for the MCM42D below remains unchanged regardless of the date code.
For all MCM42C, the location of the local memory is different from that of the MCM42D. In addition, for proper
use of the memory, it is necessary to understand how the memory is controlled.
For product manufactured with date codes newer than 0131, the following applies to the MCM42C only: The
entire memory array is controlled by LSTRB0. The value to be loaded to the STRB ACTIVE area (bits 28–24)
should be 11110 (binary). This will require a code change for customers who developed code intended for use
with MCM42C devices manufactured with date codes older than 0131.
For the MCM42D, LSTRB0 controls the entire 128K. The default value loaded into the STRB ACTIVE area of
the LMICR after reset is sufficient to control the memory. The default value is 11110, and tells the C40 that the
entire local memory is controlled by LSTRB0.
This subject is discussed in depth in Chapter 9 of the 1996 TMS320C4x User’s Guide (literature number
SPRU063). In particular, section 9.3 discusses the proper use of the memory interface control registers.
reference documentation and data sheet scope
The SMJ320MCM42 is qualified to MIL-PRF-38535. Electrical continuity of the module is ensured through the
use of IEEE-1149.1-compatible boundary-scan testing and functional checkout of the local SRAM space.
KGD refers to TI known-good-die strategy. TI KGDs are fully tested over the military temperature range per
MIL-PRF-38535 QML. Electrical tests ensure compliance of the C40 KGD components to the SMJ320C40 data
sheet (literature number SGUS017) over the operating temperature range. Module timings are virtually
unchanged from the SMJ320C40 data sheet timings. An SMJ320C40 data sheet is provided for customer
reference only and does not imply MCM compliance to published timings.
For a description of the C40 operation and application information, see the TMS320C4x User’s Guide (literature
number SPRU063).
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| SM320VC33GNMM150EP | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC EP Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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