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參數(shù)資料
| 型號(hào)： | SLA24C64-S |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 中文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, DSO-8 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 358K |
| 代理商： | SLA24C64-S |
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SLx 24C64
Semiconductor Group
9
Preliminary 1998-07-27
4
After a START condition, the master always transmits a command byte CSW or CSR.
After the acknowledge of the EEPROM control bytes follow, their contents and the
transmitter depend on the previous command byte. The description of the command and
control bytes is shown in
table 2
.
Device Addressing and EEPROM Addressing
The device has an internal address counter which points to the current EEPROM
address.
The address counter is incremented
– after a data byte to be written has been acknowledged, during entry of further data
byte
– during a byte read, thus the address counter points to the following address after
reading a data byte.
The timing conventions for read and write operations are described in
figures 5
and
6
.
Command Byte
Selects one of the 8 addressable slave devices:
The chip select
bits CS2, CS1 and CS0 (bit positions b3 to b1) are compared to their
corresponding hard wired input pins CS2, CS1 and CS0,
respectively.
Selects operation:
the least significant bit b0 is low for a write
operation (Chip Select Write Command Byte, CSW) or set high for
a read operation (Chip Select Read Command Byte, CSR).
Following CSW (b0 = 0):
The address bytes AHI/ALO containing
the address bits A0 to A12 are transmitted by the master.
Following CSR (b0 = 1):
The EEPROM transmits the read out data.
EEPROM data are read as long as the master pulls down SDA after
each byte in order to acknowledge the transfer. The read operation
is stopped by the master by releasing SDA (no acknowledge is
applied) followed by a STOP condition.
Control Bytes
Table 2
Command and Control Byte for
I
2
C-Bus Addressing of Chip and EEPROM
Command
Definition
b7
b6
b5
b4
CSW
1
0
1
0
CS2 CS1 CS0
CSR
1
0
1
0
CS2 CS1 CS0
AHI
0
0
0
A12
ALO
A7
A6
A5
A4
DATA
D7
D6
D5
D4
Function
b3
b2
b1
0
1
A8
A0
D0
chip select for write
chip select for read
high address
low address
data byte
A11
A3
D3
A10
A2
D2
A9
A1
D1
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