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參數(shù)資料
| 型號(hào)： | SLA24C64-S |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| 中文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | PLASTIC, DSO-8 |
| 文件頁數(shù)： | 19/26頁 |
| 文件大?。?/td> | 358K |
| 代理商： | SLA24C64-S |
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SLx 24C64
Semiconductor Group
19
Preliminary 1998-07-27
7.1
The bits of the protection memory can be addressed directly for reading or programming.
A protection bit address corresponds to the lowest address within the respective page
(A5 to A12, A0 to A4 = zero). The status of each protection bit is sensed internally. A
written state (“0”) prevents programming in the associated page. If an already protected
memory page is accidentally addressed for programming, the programming procedure
is suppressed.
The conventional
I
2
C-Bus protocol allows data bytes to be read and programmed only.
Therefore an independent instruction sequence for addressing and manipulation of
protection bits is implemented. For protection bit instructions the command byte CSW
with its preceding START condition followed by the associated address bytes have to be
entered twice (
figures 15
through
17
). The first command byte CSW is followed by the
address bytes AHI/ALO with the bit/page address A0 through A4 always at zero. The
second CSW is required for entering a control byte CTx for protection bit manipulation.
The three control bytes for read, write or erase of a protection bit are listed below
(
table 3
):
Protection Bit Handling
Table 3
Control Byte for Protection Bit Manipulation
Address
Name
b7
b6
CTR
x
x
CTW
x
x
CTE
x
x
Definition
b4
x
x
x
Function
b5
x
x
x
b3
x
x
x
b2
x
x
x
b1
0
0
1
b0
0
1
1
Protection bit read
Protection bit write
Protection bit erase
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