參數(shù)資料
型號(hào)： SLA24C64-S
廠商： SIEMENS A G
元件分類： DRAM
英文描述： 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
中文描述： 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝： PLASTIC, DSO-8
文件頁(yè)數(shù)： 18/26頁(yè)
文件大?。?/td> 358K
代理商： SLA24C64-S
SLx 24C64
Semiconductor Group
18
Preliminary 1998-07-27
7
The page protection mode is supported by the SLx 24C64.../P types only. For example
SLA 24C64-D/P has the same functionality as SLA 24C64-D enhanced by page
protection mode.
Each page (32 bytes) in the data memory can be protected against unintended data
changes by an associated protection bit. The protection bit memory consists of an
additional EEPROM of 256 bit (
figure 14
).
Data in the data memory can be modified only if the assigned protection bit is erased
(logical state “1”). After writing the data bytes to a page, the protection is achieved by
writing the associated protection bit (logical state “0”). Further changes in the data in a
protected page is possible only after erasing the protection bit.
Page Protection Mode
TM
Figure 14
Data Page and Assigned Protection Memory
A special procedure to write or erase a protection bit guarantees proper activation or
deactivation of page protection. For protection bit write or erase all 32 data bytes of the
respective page have to be entered for verification. The data then are compared
internally with the data to be protected. In case of identity the protection bit is written or
erased respectively.
1
0
2
3
.
.
.
0
1
2
3
n
Page 0
Page 1
Page 2
Page 3
Page n
Byte
Bit
IED02521
Data Memory Area
P
31
. . .
.
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SLA24C64-S-3/P 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus
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