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參數(shù)資料
| 型號(hào)： | SK12439PJT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 18/18頁(yè) |
| 文件大?。?/td> | 233K |
| 代理商： | SK12439PJT |
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9
Revision 1/February 9, 2001
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK12439
ADVANCED
Application Information (continued)
Figure 5.
Power Supply Filter
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. A 100
H choke will show a significant impedance at 10 kHz
frequencies and above. Because of the current draw and
the voltage that must be maintained on the PLL_VCC pin,
a low DC resistance inductor is required (less than 15
).
Generally, the resistor/capacitor filter will be cheaper, easier
to implement, and provide an adequate level of supply
filtering.
The SK12439 provides sub-nanosecond output edge
rates, therefore a good power supply bypassing scheme
is a must. Figure 6 shows a representative board layout
for the SK12439. There exist many different potential
board layouts, and the one pictured is but one. The
important aspect of the layout in Figure 6 is the low
impedance connections between VCC and GND for the
bypass capacitors.
Combining good quality general
purpose chip capacitors with good PCB layout techniques
will produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current
for the 12439 outputs. It is imperative that low inductance
chip capacitors are used. It is equally important that the
board layout does not introduce back all of the inductance
saved by using the leadless capacitors. Thin interconnect
traces between the capacitor and the power plane should
be avoided and multiple large vias should be used to tie
the capacitors to the buried power planes. Fat interconnect
and large vias will help to minimize layout induced
inductance and thus maximize the series resonant point
of the bypass capacitors.
3.3V or 5.0V
RS= 10– 15W
SK12439
PLL_VCC
VCC
0.01 F
22 F
Figure 6.
PCB Board Layout for SK12439
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit, and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystals as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of
the crystal to ensure a stable, jitter-free interface between
the crystal and the on-board oscillator.
Although the SK12439 has several design features to
minimize the susceptibility to power supply noise (isolated
power and ground and fully differential PLL), there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise-
related problems in most designs.
Jitter Performance of the SK12439
The SK12439 exhibits long term and cycle-to-cycle jitter
which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility one gets with
a synthesizer over a fixed frequency oscillator.
1
= VCC
= GND
= Via
R1
C3
C1
C2
Xtal
R1 = 10 15W
C1 = 0.01 F
C2 = 22 F
C3 = 0.1 F
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