- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98081 > SK12439PJT 800 MHz, OTHER CLOCK GENERATOR, PQCC28 PDF資料下載
參數(shù)資料
| 型號： | SK12439PJT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 233K |
| 代理商： | SK12439PJT |
5
Revision 1/February 9, 2001
www.semtech.com
HIGH-PER.ORMANCE PRODUCTS
SK12439
ADVANCED
Application Information
Programming the device amounts to properly configuring
the internal dividers to produce the desired frequency at
the outputs. The output frequency can be represented by
this formula:
FOUT = FXTAL x M x 2 ÷ N
(1)
Where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that
it is possible to select values of M such that the PLL is
unable to achieve loop lock. To avoid this, always make
sure that M is selected to be 25 - M - 50 for a 16 MHz
input reference.
For input references other than 16 MHz, the valid M values
can be calculated from the valid VCO range of 400–800
MHz.
Assuming that a 16 MHz reference frequency is used,
the above equation reduces to:
FOUT = 16 x M ÷ N
Substituting the four values for N (1, 2, 4, 8) yields:
From these ranges, the user will establish the value of N
required, then the value of M can be calculated based on
the appropriate equation above. For example, if an output
frequency of 384 MHz was desired, the following steps
would be taken to identify the appropriate M and N values.
384 MHz falls within the frequency range set by an N
value of 2, so N [1:0] = 00. For N = 2, FOUT = 8M and
M = FOUT ÷ 8.
Therefore, M = 384 ÷ 8 = 48, so
M[6:0] = 0110000.
For input reference frequencies other than 16 MHz, the
set of appropriate equations can be deduced from Equation
1. For computer applications, another useful frequency
base would be 16.666 MHz. From this reference, one
NT
U
O
.e
g
n
a
R
y
c
n
e
u
q
e
r
.
t
u
p
t
u
O
1
2
4
8
M
x
6
1
M
x
8
M
x
4
M
x
2
z
H
M
0
8
0
4
z
H
M
0
4
0
2
z
H
M
0
2
0
1
z
H
M
0
1
0
5
can generate a family of output frequencies at multiples
of the 33.333 MHz PCI clock. As an example, to generate
a 533.333 MHz clock from a 16.666 MHz reference, the
following M and N values would be used:
FOUT = 16.666 x M ÷ N
Let N = 1, M = 533.333 ÷ 16.666 = 32
The value for M falls within the constraints set for PLL
stability (400 ÷ 16.666 - M - 800 ÷ 16.666; 24 - M
- 48), therefore N[1:0] = 11 and M[6:0] = 0100000.
If the value for M fell outside of the valid range, a different
N value would be selected to try to move M in the
appropriate direction.
The M and N counters can be loaded either through a
parallel or serial interface.
The parallel interface is
controlled via the P_LOAD* signal such that a LOW to HIGH
transition will latch the information present on the M[6:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD* signal is LOW, the input latches will be
transparent, and any changes on the M[6:0] and N[1:0]
inputs will affect the FOUT output pair. To use the serial
port, the S_CLOCK signal samples the information on the
S_DATA line and loads it into a 12-bit shift register. Note
that the P_LOAD* signal must be HIGH for the serial load
operation to function. The test register is loaded with the
first three bits, the N register with the next two, and the M
register with the final eight bits of the data stream on the
S_DATA input. For each register, the most significant bit
is loaded first (T2, N1, and M6). A pulse on the S_LOAD
pin after the shift register is fully loaded will transfer the
divide values into the counters.
The HIGH and LOW
transition on the S_LOAD input will latch the new divide
values into the counters. Figure 3 illustrates the timing
diagram for both a parallel and a serial load of the
SK12439 synthesizer.
M[6:0] and N[1:0] are normally specified once at power-
up through the parallel interface, and then possibly again
through the serial interface. This approach allows the
application to come up at one frequency and then change
or fine-tune the clock as the ability to control the serial
interface becomes available.
Program Interface
Output .requency Range
相關PDF資料 |
PDF描述 |
|---|---|
| SL15100ZIT-XXX | 200 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| SL15100ZCT-XXX | 200 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| SL15102DI-XXX | OTHER CLOCK GENERATOR, DSO8 |
| SL15300EZCT-XXX | 200 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| SL15300EZI-XXX | 200 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SK125 | 制造商:Thomas & Betts 功能描述: |
| SK1250C | 制造商:DEC 制造商全稱:DEC 功能描述:12 AMP SCHOTTKY BARRIER RECTIFIERS |
| SK12516 | 制造商:Cooper Wiring Devices 功能描述: |
| SK1260C | 制造商:DEC 制造商全稱:DEC 功能描述:12 AMP SCHOTTKY BARRIER RECTIFIERS |
| SK1270C | 制造商:DEC 制造商全稱:DEC 功能描述:12 AMP SCHOTTKY BARRIER RECTIFIERS |
發(fā)布緊急采購，3分鐘左右您將得到回復。