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參數(shù)資料
| 型號： | SiI161ACT100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiI 161A PanelLink Receiver |
| 中文描述： | 精工161A條PanelLink接收機 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 260K |
| 代理商： | SII161ACT100 |
S ilic on Image, Inc .
SiI 161
A
SiI
-DS-0009-D
S ilic on Image, Inc .
9
Subject to Change without Notice
Output Pins Description
Pin
Name
QE23-
QE0
Diagram
Pin #
Type Description
See
SiI
161
A
Pin
Out
Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode
and to the first 24-bit pixel data for 2-pixels/clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Signal Mapping application note (Si
I
/AN-0007) which tabulates the
relationship between the input data to the transmitter and output data from the
receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state)
mode. A weak internal pull-down device brings each output to ground.
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock
mode.
During 1-pixel/clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Signal Mapping application note (
SiI
/AN-0007) which tabulates the
relationship between the input data to the transmitter and output data from the
receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state)
mode. A weak internal pull-down device brings each output to ground.
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on
PD or PDO will put the output driver into a high impedance (tri-state) mode. A weak
internal pull-down device brings the output to ground.
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies
active display time and a LOW level signifies blanking time. This output signal is
synchronized with the output data. A low level on PD or PDO will put the output driver
into a high impedance (tri-state) mode. A weak internal pull-down device brings the
output to ground. In Dual Link Applications, the DE output pin of the Master is
connected to the SYNC input pin of the Slave.
Horizontal Sync input control signal.
Vertical Sync input control signal.
General output control signal 1. This output is
not
powered down by PDO.
General output control signal 2.
General output control signal 3.
A low level on PD or PDO will put the output drivers (except CTL1 by PDO) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to
ground.
QO23-
QO0
See
SiI
161
A
Pin
Diagram
Out
ODCK
44
Out
DE
46
Out
HSYNC
VSYNC
CTL1
CTL2
CTL3
48
47
40
41
42
Out
Out
Out
Out
Out
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